From owner-svn-soc-all@freebsd.org Tue Jul 14 09:38:42 2015 Return-Path: Delivered-To: svn-soc-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1D1F599CFCC for ; Tue, 14 Jul 2015 09:38:42 +0000 (UTC) (envelope-from mihai@FreeBSD.org) Received: from socsvn.freebsd.org (socsvn.freebsd.org [IPv6:2001:1900:2254:206a::50:2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E86DFF05 for ; Tue, 14 Jul 2015 09:38:41 +0000 (UTC) (envelope-from mihai@FreeBSD.org) Received: from socsvn.freebsd.org ([127.0.1.124]) by socsvn.freebsd.org (8.15.2/8.15.2) with ESMTP id t6E9cfsf065273 for ; Tue, 14 Jul 2015 09:38:41 GMT (envelope-from mihai@FreeBSD.org) Received: (from www@localhost) by socsvn.freebsd.org (8.15.2/8.15.2/Submit) id t6E9ceNR065258 for svn-soc-all@FreeBSD.org; Tue, 14 Jul 2015 09:38:40 GMT (envelope-from mihai@FreeBSD.org) Date: Tue, 14 Jul 2015 09:38:40 GMT Message-Id: <201507140938.t6E9ceNR065258@socsvn.freebsd.org> X-Authentication-Warning: socsvn.freebsd.org: www set sender to mihai@FreeBSD.org using -f From: mihai@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r288365 - soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jul 2015 09:38:42 -0000 Author: mihai Date: Tue Jul 14 09:38:39 2015 New Revision: 288365 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=288365 Log: soc2015: mihai: bhyve: sys: arm: vmm: hyp.S: set VTCR configuration Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S ============================================================================== --- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S Tue Jul 14 09:37:38 2015 (r288364) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S Tue Jul 14 09:38:39 2015 (r288365) @@ -185,16 +185,10 @@ bic r0, r0, r1 mcr p15, 4, r0, c2, c0, 2 @ HTCR - @ TODO configure the VTCR for supporting 32/40 bit IPA -/* - mrc p15, 4, r1, c2, c1, 2 @ VTCR - ldr r2, =VTCR_MASK - bic r1, r1, r2 - bic r0, r0, #(~VTCR_HTCR_SH) @ clear non-reusable HTCR bits - orr r1, r0, r1 - orr r1, r1, #(VTCR_SL_L1 | VTCR_T0SZ | KVM_VTCR_S) - mcr p15, 4, r1, c2, c1, 2 @ VTCR -*/ + @ VTCR for supporting only 32 bit IPA [see VMM_VTCR_T0SZ in hyp.h] + ldr r0, =(VTCR_RES | VTCR_SL_L1 | VMM_VTCR_T0SZ | VMM_VTCR_S) + mcr p15, 4, r0, c2, c1, 2 @ VTCR + @ Set the HMAIR0/1 (same as MAIR0/1) registers for AttrIndx[2:0] ldr r0, =HMAIR0 mcr p15, 4, r0, c10, c2, 0 Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h ============================================================================== --- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Tue Jul 14 09:37:38 2015 (r288364) +++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h Tue Jul 14 09:38:39 2015 (r288365) @@ -50,6 +50,7 @@ #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) /* Virtualization Translation Control Register (VTCR) bits */ +#define VTCR_RES (1 << 31) #define VTCR_SH0 (3 << 12) #define VTCR_ORGN0 (3 << 10) #define VTCR_IRGN0 (3 << 8) @@ -58,8 +59,12 @@ #define VTCR_T0SZ (0xf) #define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | VTCR_S | VTCR_T0SZ) #define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) -#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ #define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ +/* Stage 2 address input size is 2^(32-VTCR T0SZ) (ARM - B4.1.159) */ +#define VMM_IPA_LEN 32 +#define VMM_VTCR_T0SZ ((32 - VMM_IPA_LEN) & VTCR_T0SZ) +/* The sign bit VTCR.S = VTCR.T0SZ[4] */ +#define VMM_VTCR_S (((VMM_VTCR_T0SZ) << 1) & VTCR_S) /* Hyp Configuration Register (HCR) bits */ #define HCR_TGE (1 << 27)