From owner-freebsd-arch@FreeBSD.ORG Sun Sep 14 18:16:40 2014 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1C406BDE for ; Sun, 14 Sep 2014 18:16:40 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C50B23BA for ; Sun, 14 Sep 2014 18:16:39 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.82 (FreeBSD)) (envelope-from ) id 1XTELk-000CjK-31; Sun, 14 Sep 2014 22:16:36 +0400 Date: Sun, 14 Sep 2014 22:16:36 +0400 From: Slawa Olhovchenkov To: Konstantin Belousov Subject: Re: Intel MPX (Skylake ISA) support? Message-ID: <20140914181636.GA47783@zxy.spb.ru> References: <20140913162059.GU2737@kib.kiev.ua> <20140914090033.GA2737@kib.kiev.ua> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20140914090033.GA2737@kib.kiev.ua> User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false Cc: Carsten Mattner , freebsd-arch@freebsd.org X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Sep 2014 18:16:40 -0000 On Sun, Sep 14, 2014 at 12:00:33PM +0300, Konstantin Belousov wrote: > On Sat, Sep 13, 2014 at 09:47:10PM +0200, Carsten Mattner wrote: > > On Sat, Sep 13, 2014 at 6:20 PM, Konstantin Belousov > > wrote: > > > On Sat, Sep 13, 2014 at 12:45:16PM +0200, Carsten Mattner wrote: > > >> Are there any plans to include the necessary (kernel, libc) support for > > >> Intel MPX (https://en.wikipedia.org/wiki/Intel_MPX)? > > > > > > I looked at this several times. The 319433 (Instructions Set Extensions > > > prog reference) even at the current revision 20 still seems to not provide > > > the complete documentation on the CPU side. E.g., could you point me at > > > the description of the save area for MPX ? It is required since usermode > > > bndcfg register can only be set by restoring from the XSAVE area. > > > > > > That said, I believe that most, if not all, of the needed kernel-side > > > support is already there by the generic XSAVE code. > > > > > > I never see any specification of runtime services expected by the code > > > generated by mpx-enabled gcc. > > > > Is https://lkml.org/lkml/2014/9/11/182 helpful? > > Not for me. I have zero interest in reverse-engineering Linux code > for core CPU functionality. Intel usually provides high-quality > documentation for the processors, and I hope that they will provide all > needed information together with the hardware release. > > Another significant missing piece is the lack of description of the > initial state and expectation of the runtime support in the ABI > document. The ABI draft 0.3 from July 17, 2013, specially edited for > MPX, only talks about argument passing conventions and dwarf, it seems. > > It is curious discussion about non-feasibility of implementing MPX > translation tables in usermode. Just for fun, I will try to do > something purely in usermode (when/if hardware will be available). https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf Cgapter 9. Total 30 pages. Also Intel SDE available.