From owner-svn-src-all@FreeBSD.ORG Thu Feb 19 14:39:53 2009 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 68CE91065675; Thu, 19 Feb 2009 14:39:53 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 3C7808FC24; Thu, 19 Feb 2009 14:39:53 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n1JEdq29099734; Thu, 19 Feb 2009 14:39:52 GMT (envelope-from avg@svn.freebsd.org) Received: (from avg@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n1JEdqRM099733; Thu, 19 Feb 2009 14:39:52 GMT (envelope-from avg@svn.freebsd.org) Message-Id: <200902191439.n1JEdqRM099733@svn.freebsd.org> From: Andriy Gapon Date: Thu, 19 Feb 2009 14:39:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r188814 - head/sys/dev/acpica X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Feb 2009 14:39:53 -0000 Author: avg Date: Thu Feb 19 14:39:52 2009 New Revision: 188814 URL: http://svn.freebsd.org/changeset/base/188814 Log: acpi_cpu: fixup for PIIX4E PCI config related to C2 This is triggered only if BIOS configures ACPI_BITREG_BUS_MASTER_RLD aka BRLD_EN_BM to 1. Rationale: 1. we do not support C3 on PIIX4E 2. bus master activity need not break out of C2 state 3. because of CPU_QUIRK_NO_BM_CTRL quirk we may reset bus master status which would result in immediate break out from C2 So if you have seen cpu0: too many short sleeps, backing off to C1 with this chipset before you may want to try cx_lowest of C2 again. Reviewed by: rpaulo (mentor), njl Approved by: rpaulo (mentor) Modified: head/sys/dev/acpica/acpi_cpu.c Modified: head/sys/dev/acpica/acpi_cpu.c ============================================================================== --- head/sys/dev/acpica/acpi_cpu.c Thu Feb 19 13:45:25 2009 (r188813) +++ head/sys/dev/acpica/acpi_cpu.c Thu Feb 19 14:39:52 2009 (r188814) @@ -1082,6 +1082,10 @@ acpi_cpu_quirks(void) * * Also, make sure that all interrupts cause a "Stop Break" * event to exit from C2 state. + * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) + * should be set to zero, otherwise it causes C2 to short-sleep. + * PIIX4 doesn't properly support C3 and bus master activity + * need not break out of C2. */ case PCI_REVISION_A_STEP: case PCI_REVISION_B_STEP: @@ -1094,10 +1098,16 @@ acpi_cpu_quirks(void) val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { ACPI_DEBUG_PRINT((ACPI_DB_INFO, - "PIIX4: enabling IRQs to generate Stop Break\n")); + "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); val |= PIIX4_STOP_BREAK_MASK; pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); } + AcpiGetRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); + if (val) { + ACPI_DEBUG_PRINT((ACPI_DB_INFO, + "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); + AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); + } break; default: break;