From owner-freebsd-current@FreeBSD.ORG Wed Jun 16 10:18:21 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id B2A6916A4CF for ; Wed, 16 Jun 2004 10:18:21 +0000 (GMT) Received: from salvador.pacific.net.sg (salvador.pacific.net.sg [203.120.90.219]) by mx1.FreeBSD.org (Postfix) with SMTP id A037143D1D for ; Wed, 16 Jun 2004 10:18:20 +0000 (GMT) (envelope-from oceanare@pacific.net.sg) Received: (qmail 25539 invoked from network); 16 Jun 2004 10:18:06 -0000 Received: from unknown (HELO maxwell2.pacific.net.sg) (203.120.90.192) by salvador with SMTP; 16 Jun 2004 10:18:06 -0000 Received: from pacific.net.sg ([210.24.202.26]) by maxwell2.pacific.net.sg with ESMTP id <20040616101805.ZFLO5345.maxwell2.pacific.net.sg@pacific.net.sg>; Wed, 16 Jun 2004 18:18:05 +0800 Message-ID: <40D01E59.8000404@pacific.net.sg> Date: Wed, 16 Jun 2004 18:18:01 +0800 From: Erich Dollansky Organization: oceanare pte ltd User-Agent: Mozilla/5.0 (X11; U; FreeBSD i386; en-US; rv:1.7b) Gecko/20040409 X-Accept-Language: en-us, en MIME-Version: 1.0 To: Martin Nilsson References: <20040616112758.46677e25@Magellan.Leidinger.net> <40D016F2.2080904@gneto.com> In-Reply-To: <40D016F2.2080904@gneto.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit cc: Alexander Leidinger cc: current@freebsd.org Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2004 10:18:21 -0000 Hi, Martin Nilsson wrote: > Alexander Leidinger wrote: > > How much effct on performance does a wrong cache size value have? > The effect depends very much on the application and its ability to use the CPU cache. I did some benchmarks to get a feeling for it on Athlon MPs some time ago. The improvement in speed was up to factor 30 under high CPU load for very data intense operations. Applications even could become slower if the CPU cache holds the data anyway. The reason is the additional effort to prefetch data which is already chached. It is not this easy to use always the right strategy to get the right data into the cache. Erich