From owner-freebsd-current@FreeBSD.ORG Wed Jun 16 10:45:29 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id BDC2216A4EE for ; Wed, 16 Jun 2004 10:45:29 +0000 (GMT) Received: from mailout09.sul.t-online.com (mailout09.sul.t-online.com [194.25.134.84]) by mx1.FreeBSD.org (Postfix) with ESMTP id D4AC143D62 for ; Wed, 16 Jun 2004 10:45:27 +0000 (GMT) (envelope-from Alexander@Leidinger.net) Received: from fwd03.aul.t-online.de by mailout09.sul.t-online.com with smtp id 1BaXue-0000Cf-02; Wed, 16 Jun 2004 12:45:00 +0200 Received: from Andro-Beta.Leidinger.net (TF8c1+ZbQeLG0kvcqEX+i2dlQDjtCQ0hoRHcOP66O6I3FHFjdU+dZp@[217.229.221.168]) by fmrl03.sul.t-online.com with esmtp id 1BaXuK-0l30oC0; Wed, 16 Jun 2004 12:44:40 +0200 Received: from Magellan.Leidinger.net (Magellan.Leidinger.net [192.168.1.1]) i5GAioaa053089; Wed, 16 Jun 2004 12:44:50 +0200 (CEST) (envelope-from Alexander@Leidinger.net) Date: Wed, 16 Jun 2004 12:46:30 +0200 From: Alexander Leidinger To: Bruce M Simpson Message-Id: <20040616124630.34c80d7a@Magellan.Leidinger.net> In-Reply-To: <20040616101102.GQ32244@empiric.dek.spc.org> References: <20040616112758.46677e25@Magellan.Leidinger.net> <40D016F2.2080904@gneto.com> <20040616101102.GQ32244@empiric.dek.spc.org> X-Mailer: Sylpheed version 0.9.11claws (GTK+ 1.2.10; i386-portbld-freebsd5.2) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Seen: false X-ID: TF8c1+ZbQeLG0kvcqEX+i2dlQDjtCQ0hoRHcOP66O6I3FHFjdU+dZp@t-dialin.net X-Mailman-Approved-At: Wed, 16 Jun 2004 11:49:41 +0000 Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2004 10:45:30 -0000 On Wed, 16 Jun 2004 11:11:02 +0100 Bruce M Simpson wrote: > On Wed, Jun 16, 2004 at 11:46:26AM +0200, Martin Nilsson wrote: > > The more expensive intel processors also have L3 caches of 1-4MB. > > Since intels processors are built with inclusive caches (data in L2 > > cache is also present in L3) shouldn't the value used be that of the > > largest cache be it L2 or L3? > > > > How much effct on performance does a wrong cache size value have? > > Gag. I posted something on this whole subject last *year*, and still > haven't gotten round to code. I found it: http://unix.derkeiler.com/Mailing-Lists/FreeBSD/hackers/2003-06/0462.html Bye, Alexander. -- I'm available to get hired (preferred in .lu). http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7