From owner-freebsd-hackers  Mon Dec  7 14:07:40 1998
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From: Robert Nordier <rnordier@nordier.com>
Message-Id: <199812072205.AAA01520@ceia.nordier.com>
Subject: Re: How could this work?
In-Reply-To: <199812072032.NAA05466@harmony.village.org> from Warner Losh at "Dec 7, 98 01:32:18 pm"
To: imp@village.org (Warner Losh)
Date: Tue, 8 Dec 1998 00:05:45 +0200 (SAT)
Cc: rnordier@nordier.com, hackers@FreeBSD.ORG
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Warner Losh wrote:
> In message <199812072031.WAA00262@ceia.nordier.com> Robert Nordier writes:
> : IIRC, reads and writes involving port 0xb2 are done for their
> : side-effects (to cause an SMI, put CPU into sleep mode, etc).
> 
> I guess I'm asking how this happens?  Can you provide more details, or
> a pointer to same?

Any read from the APM control register (port 0xb2 for certain
chipsets) causes STPCLK# to be asserted, and the CPU goes into
Stop-Grant State, from where it can enter Sleep State or return
to Normal State.

The Pentium II Processor Developer's Manual, Chapter 7, covers
SMI#, STPCLK#, SLP#, etc; and there's a description of SMM in Vol.
III of the Intel Architecture Software Developer's Manual.  (Both
available in acrobat format at the Intel web site literature center.)

--
Robert Nordier

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