From owner-freebsd-i386@FreeBSD.ORG Wed Apr 18 09:20:09 2007 Return-Path: X-Original-To: freebsd-i386@hub.freebsd.org Delivered-To: freebsd-i386@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 3860B16A402 for ; Wed, 18 Apr 2007 09:20:09 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [69.147.83.40]) by mx1.freebsd.org (Postfix) with ESMTP id 28B0913C4AD for ; Wed, 18 Apr 2007 09:20:09 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (gnats@localhost [127.0.0.1]) by freefall.freebsd.org (8.13.4/8.13.4) with ESMTP id l3I9K909067221 for ; Wed, 18 Apr 2007 09:20:09 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.13.4/8.13.4/Submit) id l3I9K8ZU067218; Wed, 18 Apr 2007 09:20:08 GMT (envelope-from gnats) Date: Wed, 18 Apr 2007 09:20:08 GMT Message-Id: <200704180920.l3I9K8ZU067218@freefall.freebsd.org> To: freebsd-i386@FreeBSD.org From: Ariff Abdullah Cc: Subject: Re: i386/104678: SMP not working on Turion XP Laptop X-BeenThere: freebsd-i386@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: Ariff Abdullah List-Id: I386-specific issues for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Apr 2007 09:20:09 -0000 The following reply was made to PR i386/104678; it has been noted by GNATS. From: Ariff Abdullah To: Rainer Alves Cc: bug-followup@FreeBSD.org, bde@zeta.org.au, danolson@visi.com, infofarmer@FreeBSD.org, kpitcher@KeithPitcher.com Subject: Re: i386/104678: SMP not working on Turion XP Laptop Date: Wed, 18 Apr 2007 17:11:42 +0800 This is a multi-part message in MIME format. --Multipart=_Wed__18_Apr_2007_17_11_42_+0800_kNcDcPgVc_KH17AH Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 18 Apr 2007 04:50:11 GMT Rainer Alves wrote: > > I've been using your idle_cpu_* patches for about 6 months and > experienced some minor gliches (system would panic/hang once in a > while). Your new patch seems a lot simpler, and is working > perfectly here so far. Thanks! > This one should become the final patch (if nobody complains about it). More thorough check on processor models/revisions especially for possible future production. Please backout previous patches first before applying this one. -- Ariff Abdullah FreeBSD ... Recording in stereo is obviously too advanced and confusing for us idiot ***** users :P ........ --Multipart=_Wed__18_Apr_2007_17_11_42_+0800_kNcDcPgVc_KH17AH Content-Type: text/x-diff; name="k8_c1e.diff" Content-Disposition: attachment; filename="k8_c1e.diff" Content-Transfer-Encoding: 7bit Index: src/sys/amd64/amd64/initcpu.c =================================================================== RCS file: /home/ncvs/src/sys/amd64/amd64/initcpu.c,v retrieving revision 1.50 diff -u -r1.50 initcpu.c --- src/sys/amd64/amd64/initcpu.c 19 Jun 2006 22:59:28 -0000 1.50 +++ src/sys/amd64/amd64/initcpu.c 18 Apr 2007 08:52:10 -0000 @@ -79,4 +79,28 @@ wrmsr(MSR_EFER, msr); pg_nx = PG_NX; } + if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { + /* + * Detect the present of C1E capability mostly on latest + * dual-cores (or future) k8 family. This feature render the + * apic timer dead, and we disable it by reading Interrupt + * Pending Message register and unset both C1eOnCmpHalt + * (bit 28) and SmiOnCmpHalt (bit 27). + * + * Reference: + * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh + * Processors" + * #32559 revision 3.00 + */ + if (((cpu_id & 0x00000f00) == 0x00000f00 && + ((cpu_id & 0x000f0000) >= 0x00040000 || + (cpu_id & 0x0ff00000) > 0x00000000)) || + (cpu_id & 0x00000f00) > 0x00000f00) { + msr = rdmsr(0xc0010055) & 0x1fffffffULL; + if (msr & 0x18000000) { + msr &= ~0x18000000ULL; + wrmsr(0xc0010055, msr); + } + } + } } Index: src/sys/i386/i386/initcpu.c =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/initcpu.c,v retrieving revision 1.56 diff -u -r1.56 initcpu.c --- src/sys/i386/i386/initcpu.c 6 Apr 2007 18:15:02 -0000 1.56 +++ src/sys/i386/i386/initcpu.c 18 Apr 2007 08:52:10 -0000 @@ -658,6 +658,31 @@ break; } } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { + /* + * Detect the present of C1E capability mostly on + * latest dual-cores (or future) k8 family. This + * feature render the apic timer dead, and we disable + * it by reading Interrupt Pending Message register + * and unset both C1eOnCmpHalt (bit 28) and + * SmiOnCmpHalt (bit 27). + * + * Reference: + * "BIOS and Kernel Developer's Guide for AMD NPT + * Family 0Fh Processors" + * #32559 revision 3.00 + */ + if (((cpu_id & 0x00000f00) == 0x00000f00 && + ((cpu_id & 0x000f0000) >= 0x00040000 || + (cpu_id & 0x0ff00000) > 0x00000000)) || + (cpu_id & 0x00000f00) > 0x00000f00) { + u_int64_t msr; + + msr = rdmsr(0xc0010055) & 0x1fffffffULL; + if (msr & 0x18000000) { + msr &= ~0x18000000ULL; + wrmsr(0xc0010055, msr); + } + } #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) /* * Sometimes the BIOS doesn't enable SSE instructions. --Multipart=_Wed__18_Apr_2007_17_11_42_+0800_kNcDcPgVc_KH17AH--