From owner-svn-src-all@freebsd.org Thu Dec 10 17:38:10 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 280439D7899; Thu, 10 Dec 2015 17:38:10 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 08CF71C9D; Thu, 10 Dec 2015 17:38:10 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from ralph.baldwin.cx (c-73-231-226-104.hsd1.ca.comcast.net [73.231.226.104]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 46386B986; Thu, 10 Dec 2015 12:38:07 -0500 (EST) From: John Baldwin To: Andrew Turner Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r292064 - head/sys/arm64/arm64 Date: Thu, 10 Dec 2015 09:34:34 -0800 Message-ID: <2223711.lepPF7yQe2@ralph.baldwin.cx> User-Agent: KMail/4.14.3 (FreeBSD/10.2-STABLE; KDE/4.14.3; amd64; ; ) In-Reply-To: <201512101640.tBAGec5X072851@repo.freebsd.org> References: <201512101640.tBAGec5X072851@repo.freebsd.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Thu, 10 Dec 2015 12:38:07 -0500 (EST) X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Dec 2015 17:38:10 -0000 On Thursday, December 10, 2015 04:40:38 PM Andrew Turner wrote: > Author: andrew > Date: Thu Dec 10 16:40:38 2015 > New Revision: 292064 > URL: https://svnweb.freebsd.org/changeset/base/292064 > > Log: > Add support for the GICv2M extension to the GICv2 interrupt controller. > This is (oddly) specified in the ARM Server Base System Architecture. It > extends the GICv2 to support MSI and MSI-X interrupts, however only the > latter are currently supported. MSI and MSI-X only different in the config registers used to configure them in the PCI function. The on-wire format of the PCI transaction is identical, so from a PIC's perspective there should be no difference. They are all just MSI messages. This is why both MSI and MSI-X interrupt resources use the same PCIB_MAP_MSI() method to map a given IRQ to an (address, data) tuple. -- John Baldwin