From owner-svn-src-all@FreeBSD.ORG Sun Apr 19 20:15:58 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 35AC4F14; Sun, 19 Apr 2015 20:15:58 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 23B1293A; Sun, 19 Apr 2015 20:15:58 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t3JKFws3018368; Sun, 19 Apr 2015 20:15:58 GMT (envelope-from marius@FreeBSD.org) Received: (from marius@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t3JKFwm1018367; Sun, 19 Apr 2015 20:15:58 GMT (envelope-from marius@FreeBSD.org) Message-Id: <201504192015.t3JKFwm1018367@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: marius set sender to marius@FreeBSD.org using -f From: Marius Strobl Date: Sun, 19 Apr 2015 20:15:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r281751 - head/sys/x86/x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 19 Apr 2015 20:15:58 -0000 Author: marius Date: Sun Apr 19 20:15:57 2015 New Revision: 281751 URL: https://svnweb.freebsd.org/changeset/base/281751 Log: Refine the workaround for Intel HSD131 [1] added in r269052: - Use the full mask described by the erratum as with a sufficiently high number of these false-positives, the overflow bit (bit 62) additionally gets set [7]. - HSD131 has been brought into several other Haswell-derived CPUs including to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of these benign errors by default on CPU models affected by HSM142, HSW131 and BDM48 [2 - 5], describing the HSD131 silicon bug for additional models. Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered by this fault [6], with the specification update concerned with HSM142 [2] only referring to 0x3c and 0x46. Submitted by: David Froehlich [7] MFC after: 3 days http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf [1] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf [2] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf [3] http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf [4] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf [5] https://lists.freebsd.org/pipermail/freebsd-hackers/2015-January/046878.html [6] Modified: head/sys/x86/x86/mca.c Modified: head/sys/x86/x86/mca.c ============================================================================== --- head/sys/x86/x86/mca.c Sun Apr 19 20:08:36 2015 (r281750) +++ head/sys/x86/x86/mca.c Sun Apr 19 20:15:57 2015 (r281751) @@ -251,15 +251,24 @@ mca_mute(const struct mca_record *rec) { /* - * Skip spurious corrected parity errors generated by desktop Haswell - * (see HSD131 erratum) unless reporting is enabled. - * Note that these errors also have been observed with D0-stepping, - * while the revision 014 desktop Haswell specification update only - * talks about C0-stepping. + * Skip spurious corrected parity errors generated by Intel Haswell- + * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48 + * erratum respectively), unless reporting is enabled. + * Note that these errors also have been observed with the D0-stepping + * of Haswell, while at least initially the CPU specification updates + * suggested only the C0-stepping to be affected. Similarly, Celeron + * 2955U with a CPU ID of 0x45 apparently are also concerned with the + * same problem, with HSM142 only referring to 0x3c and 0x46. */ - if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL && - rec->mr_cpu_id == 0x306c3 && rec->mr_bank == 0 && - rec->mr_status == 0x90000040000f0005 && !intel6h_HSD131) + if (cpu_vendor_id == CPU_VENDOR_INTEL && + CPUID_TO_FAMILY(cpu_id) == 0x6 && + (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */ + CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */ + CPUID_TO_MODEL(cpu_id) == 0x45 || + CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */ + rec->mr_bank == 0 && + (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 && + !intel6h_HSD131) return (1); return (0);