From owner-freebsd-arm@FreeBSD.ORG Tue Sep 6 22:34:25 2011 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 889FA1065670 for ; Tue, 6 Sep 2011 22:34:25 +0000 (UTC) (envelope-from marktinguely@gmail.com) Received: from mail-gw0-f44.google.com (mail-gw0-f44.google.com [74.125.83.44]) by mx1.freebsd.org (Postfix) with ESMTP id 43CF68FC16 for ; Tue, 6 Sep 2011 22:34:24 +0000 (UTC) Received: by gwb20 with SMTP id 20so5478869gwb.17 for ; Tue, 06 Sep 2011 15:34:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=pBxQjDA7N97cxQDOETbFQHvWPesE2ImYkFixw/GgQa0=; b=XgjKcVksLT0aWjfct9m2MHZN2zD1oi12p9A0yFG+D9n8PXXVSGErieAvgjxeQEA8ua GJAauOTRLxqes2OxgLU3l1y/VyV/zM2BH4cdHaNjQpjxc8xkj5NjtoEHofbCfDPh+a71 7TPEjKhd1stUr+mOldnCzxVsdEuHQTMk/PK4I= Received: by 10.236.189.104 with SMTP id b68mr27874177yhn.13.1315346981636; Tue, 06 Sep 2011 15:09:41 -0700 (PDT) Received: from [192.168.1.111] ([206.188.254.192]) by mx.google.com with ESMTPS id t56sm1284596yhh.20.2011.09.06.15.09.40 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 06 Sep 2011 15:09:41 -0700 (PDT) Message-ID: <4E669A1E.6060307@gmail.com> Date: Tue, 06 Sep 2011 17:09:34 -0500 From: Mark Tinguely User-Agent: Mozilla/5.0 (Windows NT 5.1; rv:6.0.1) Gecko/20110830 Thunderbird/6.0.1 MIME-Version: 1.0 To: Ian Lepore References: <201109031940.p83Je9fo004190@freefall.freebsd.org> <1315342967.1671.21.camel@revolution.hippie.lan> In-Reply-To: <1315342967.1671.21.camel@revolution.hippie.lan> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: freebsd-arm Subject: Re: arm/160431: [patch] Disable interrupts during busdma cache sync operations. X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2011 22:34:25 -0000 On 9/6/2011 4:02 PM, Ian Lepore wrote: > After thinking more about Mark's question I've come to the conclusion > that interrupts should only be disabled in the partial cachline flush > case. Basically it comes down to the fact that only that case is > special, in that we temporarily duplicate the state of the hardware into > a local buffer then restore it, and we can't let the state of the real > hardware change during that time. > > It also occurs to me that if it's necessary to disable interrupts during > all cache operations done by the busdma code, then it should be just as > necessary during the operations done by the pmap code, and it's not > clear to me that those operations are all currently happening only while > interrupts are disabled. > > So, here is a do-over on the patch that only disables interrupts in the > partial cacheline case. Considering that the partial case seems to be > pretty rare, and tends to involve buffers smaller a single cacheline, > this should result in having interrupts disabled a whole lot less often > during buffer syncs. > Rant on. I am not picking on you. I hate the BUS_DMASYNC_POSTREAD code! I want it gone, gone,gone. If the page(s) is shared with another memory space, then we know the page caching will be turned off and this is not needed (and if executed anyway, it is sloooow). BUS_DMASYNC_PREREAD would be enough IF: bus_dmamem_alloc() returns cache aligned space (very easy). Force the device driver writers to cache align their buffers. We could provide a define to make it easy. Rant off. --Mark Tinguely