From owner-svn-src-all@freebsd.org Fri Apr 8 15:22:32 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 38E4FB0881F; Fri, 8 Apr 2016 15:22:32 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 10BCA15BD; Fri, 8 Apr 2016 15:22:31 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u38FMVRJ062483; Fri, 8 Apr 2016 15:22:31 GMT (envelope-from sgalabov@FreeBSD.org) Received: (from sgalabov@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u38FMVqK062482; Fri, 8 Apr 2016 15:22:31 GMT (envelope-from sgalabov@FreeBSD.org) Message-Id: <201604081522.u38FMVqK062482@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: sgalabov set sender to sgalabov@FreeBSD.org using -f From: Stanislav Galabov Date: Fri, 8 Apr 2016 15:22:31 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r297716 - head/sys/mips/mediatek X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Apr 2016 15:22:32 -0000 Author: sgalabov Date: Fri Apr 8 15:22:30 2016 New Revision: 297716 URL: https://svnweb.freebsd.org/changeset/base/297716 Log: Introduce XHCI support for MT7621 SoC Tested on a MT7621 board, similar to the WiTi board. More testing will be required to confirm everything is fine, but things look good so far. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5885 Added: head/sys/mips/mediatek/mtk_xhci.c (contents, props changed) Added: head/sys/mips/mediatek/mtk_xhci.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/mediatek/mtk_xhci.c Fri Apr 8 15:22:30 2016 (r297716) @@ -0,0 +1,298 @@ +#include +__FBSDID("$FreeBSD$"); + +/*- + * Copyright (c) 2015 Stanislav Galabov. All rights reserved. + * Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved. + * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include + +#define XHCI_HC_DEVSTR "MTK USB 3.0 controller" + +static device_probe_t mtk_xhci_fdt_probe; +static device_attach_t mtk_xhci_fdt_attach; +static device_detach_t mtk_xhci_fdt_detach; + +static void mtk_xhci_fdt_init(device_t dev); + +static int +mtk_xhci_fdt_probe(device_t self) +{ + + if (!ofw_bus_status_okay(self)) + return (ENXIO); + + if (!ofw_bus_is_compatible(self, "mtk,usb-xhci")) + return (ENXIO); + + device_set_desc(self, XHCI_HC_DEVSTR); + + return (BUS_PROBE_DEFAULT); +} + +static int +mtk_xhci_fdt_attach(device_t self) +{ + struct xhci_softc *sc = device_get_softc(self); + int err; + int rid; + + /* initialise some bus fields */ + sc->sc_bus.parent = self; + sc->sc_bus.devices = sc->sc_devices; + sc->sc_bus.devices_max = XHCI_MAX_DEVICES; + sc->sc_bus.dma_bits = 32; + + rid = 0; + sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (!sc->sc_io_res) { + device_printf(self, "Could not map memory\n"); + goto error; + } + sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); + sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); + sc->sc_io_size = rman_get_size(sc->sc_io_res); + + mtk_xhci_fdt_init(self); + + rid = 0; + sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->sc_irq_res == NULL) { + device_printf(self, "Could not allocate irq\n"); + goto error; + } + + sc->sc_bus.bdev = device_add_child(self, "usbus", -1); + if (!(sc->sc_bus.bdev)) { + device_printf(self, "Could not add USB device\n"); + goto error; + } + device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); + device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR); + + sprintf(sc->sc_vendor, "Mediatek"); + + err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); + if (err) { + device_printf(self, "Could not setup irq, %d\n", err); + sc->sc_intr_hdl = NULL; + goto error; + } + + err = xhci_init(sc, self, 1); + if (err == 0) + err = xhci_halt_controller(sc); + if (err == 0) + err = xhci_start_controller(sc); + if (err == 0) + err = device_probe_and_attach(sc->sc_bus.bdev); + if (err) { + device_printf(self, "USB init failed err=%d\n", err); + goto error; + } + return (0); + +error: + mtk_xhci_fdt_detach(self); + return (ENXIO); +} + +static int +mtk_xhci_fdt_detach(device_t self) +{ + struct xhci_softc *sc = device_get_softc(self); + device_t bdev; + int err; + + if (sc->sc_bus.bdev) { + bdev = sc->sc_bus.bdev; + device_detach(bdev); + device_delete_child(self, bdev); + } + /* during module unload there are lots of children leftover */ + device_delete_children(self); + + if (sc->sc_irq_res && sc->sc_intr_hdl) { + /* + * only call xhci_detach() after xhci_init() + */ + xhci_uninit(sc); + + err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); + if (err) + device_printf(self, "Could not tear down irq, %d\n", + err); + sc->sc_intr_hdl = NULL; + } + if (sc->sc_irq_res) { + bus_release_resource(self, SYS_RES_IRQ, 0, + sc->sc_irq_res); + sc->sc_irq_res = NULL; + } + if (sc->sc_io_res) { + bus_release_resource(self, SYS_RES_MEMORY, 0, + sc->sc_io_res); + sc->sc_io_res = NULL; + } + + return (0); +} + +static device_method_t mtk_xhci_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, mtk_xhci_fdt_probe), + DEVMETHOD(device_attach, mtk_xhci_fdt_attach), + DEVMETHOD(device_detach, mtk_xhci_fdt_detach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + DEVMETHOD_END +}; + +static driver_t mtk_xhci_fdt_driver = { + .name = "xhci", + .methods = mtk_xhci_fdt_methods, + .size = sizeof(struct xhci_softc), +}; + +static devclass_t mtk_xhci_fdt_devclass; + +DRIVER_MODULE(xhci, simplebus, mtk_xhci_fdt_driver, mtk_xhci_fdt_devclass, 0, + 0); + +#define USB_HDMA_CFG 0x950 +#define USB_HDMA_CFG_MT7621_VAL 0x10E0E0C + +#define U3_LTSSM_TIMING_PARAM3 0x2514 +#define U3_LTSSM_TIMING_VAL 0x3E8012C + +#define SYNC_HS_EOF 0x938 +#define SYNC_HS_EOF_VAL 0x201F3 + +#define USB_IP_SPAR0 0x107C8 +#define USB_IP_SPAR0_VAL 1 + +#define U2_PHY_BASE_P0 0x10800 +#define U2_PHY_BASE_P1 0x11000 +#define U2_PHYD_CR1 0x64 +#define U2_PHYD_CR1_MASK (3<<18) +#define U2_PHYD_CR1_VAL (1<<18) + +#define USB_IP_PW_CTRL 0x10700 +#define USB_IP_PW_CTRL_1 0x10704 +#define USB_IP_CAP 0x10724 +#define USB_U3_CTRL(p) (0x10730 + ((p) * 0x08)) +#define USB_U2_CTRL(p) (0x10750 + ((p) * 0x08)) + +#define USB_IP_SW_RST (1 << 0) +#define USB_IP_PDN (1 << 0) + +#define USB_PORT_DIS (1 << 0) +#define USB_PORT_PDN (1 << 1) + +#define U3_PORT_NUM(p) (p & 0xFF) +#define U2_PORT_NUM(p) ((p>>8) & 0xFF) + +#define RD4(_sc, _reg) bus_read_4((_sc)->sc_io_res, (_reg)) +#define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) +#define CLRSET4(_sc, _reg, _clr, _set) \ + WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set)) + +static void +mtk_xhci_fdt_init(device_t dev) +{ + struct xhci_softc *sc; + uint32_t temp, u3_ports, u2_ports, i; + + sc = device_get_softc(dev); + + temp = RD4(sc, USB_IP_CAP); + u3_ports = U3_PORT_NUM(temp); + u2_ports = U2_PORT_NUM(temp); + + device_printf(dev, "%d USB3 ports, %d USB2 ports\n", + u3_ports, u2_ports); + + CLRSET4(sc, USB_IP_PW_CTRL, 0, USB_IP_SW_RST); + CLRSET4(sc, USB_IP_PW_CTRL, USB_IP_SW_RST, 0); + CLRSET4(sc, USB_IP_PW_CTRL_1, USB_IP_PDN, 0); + + for (i = 0; i < u3_ports; i++) + CLRSET4(sc, USB_U3_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); + + for (i = 0; i < u2_ports; i++) + CLRSET4(sc, USB_U2_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0); + + DELAY(100000); + + WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL); + WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL); + WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL); + WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL); + CLRSET4(sc, U2_PHY_BASE_P0 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, + U2_PHYD_CR1_VAL); + CLRSET4(sc, U2_PHY_BASE_P1 + U2_PHYD_CR1, U2_PHYD_CR1_MASK, + U2_PHYD_CR1_VAL); +}