From owner-freebsd-current@FreeBSD.ORG Fri Aug 6 02:31:06 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 22E6A16A4CE; Fri, 6 Aug 2004 02:31:06 +0000 (GMT) Received: from arginine.spc.org (arginine.spc.org [195.206.69.236]) by mx1.FreeBSD.org (Postfix) with ESMTP id 5AE5043D3F; Fri, 6 Aug 2004 02:31:05 +0000 (GMT) (envelope-from bms@spc.org) Received: from localhost (localhost [127.0.0.1]) by arginine.spc.org (Postfix) with ESMTP id 9B1EB6520C; Fri, 6 Aug 2004 03:31:03 +0100 (BST) Received: from arginine.spc.org ([127.0.0.1]) by localhost (arginine.spc.org [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 99675-04; Fri, 6 Aug 2004 03:31:03 +0100 (BST) Received: from empiric.dek.spc.org (dhcp94.icir.org [192.150.187.94]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by arginine.spc.org (Postfix) with ESMTP id 4397B651FC; Fri, 6 Aug 2004 03:30:58 +0100 (BST) Received: by empiric.dek.spc.org (Postfix, from userid 1001) id ECD1962C8; Thu, 5 Aug 2004 19:30:55 -0700 (PDT) Date: Thu, 5 Aug 2004 19:30:55 -0700 From: Bruce M Simpson To: John Baldwin Message-ID: <20040806023055.GC20148@empiric.icir.org> Mail-Followup-To: John Baldwin , freebsd-current@freebsd.org, Tim Robbins , Scott Long References: <20040805050422.GA41201@cat.robbins.dropbear.id.au> <200408051759.53079.jhb@FreeBSD.org> <4112B184.8010303@samsco.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4112B184.8010303@samsco.org> cc: freebsd-current@freebsd.org cc: Tim Robbins Subject: Re: Atomic operations on i386/amd64 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Aug 2004 02:31:06 -0000 On Thu, Aug 05, 2004 at 04:15:32PM -0600, Scott Long wrote: > >>Is there any particular reason why atomic_load_acq_*() and > >>atomic_store_rel_*() are implemented with CMPXCHG and XCHG instead of > >>MOV on i386/amd64 UP? Have a look at Linux. They ended up doing a runtime self-modifying kernel hack so they could ship generic kernels which used the appropriate locking instructions on each x86 family CPU. BMS