From owner-svn-src-all@FreeBSD.ORG Sun May 31 09:07:28 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 07973A4D; Sun, 31 May 2015 09:07:28 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CF4A5127A; Sun, 31 May 2015 09:07:27 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t4V97Rfp003438; Sun, 31 May 2015 09:07:27 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t4V97RLB003435; Sun, 31 May 2015 09:07:27 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201505310907.t4V97RLB003435@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Sun, 31 May 2015 09:07:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r283807 - head/lib/libc/arm/aeabi X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 31 May 2015 09:07:28 -0000 Author: andrew Date: Sun May 31 09:07:26 2015 New Revision: 283807 URL: https://svnweb.freebsd.org/changeset/base/283807 Log: Use a register to set the cpsr bits. The ip register is safe to be changed within all of these functions, and is only stored in some to correctly pad the stack. This will be needed to build as Thumb-2 as, unlike with ARM instructions, the msr instruction only takes a register as the input. Modified: head/lib/libc/arm/aeabi/aeabi_asm_double.S head/lib/libc/arm/aeabi/aeabi_asm_float.S Modified: head/lib/libc/arm/aeabi/aeabi_asm_double.S ============================================================================== --- head/lib/libc/arm/aeabi/aeabi_asm_double.S Sun May 31 08:10:35 2015 (r283806) +++ head/lib/libc/arm/aeabi/aeabi_asm_double.S Sun May 31 09:07:26 2015 (r283807) @@ -56,7 +56,7 @@ ENTRY(__aeabi_cdcmple) cmp r0, #1 bne 1f /* Yes, clear Z and C */ - msr cpsr_c, #(0) + mov ip, #(0) b 99f 1: @@ -70,14 +70,15 @@ ENTRY(__aeabi_cdcmple) cmp r0, #1 bne 2f /* Yes, set Z and C */ - msr cpsr_c, #(PCR_Z | PCR_C) + mov ip, #(PCR_Z | PCR_C) b 99f 2: /* Not less than or equal, set C and clear Z */ - msr cpsr_c, #(PCR_C) + mov ip, #(PCR_C) 99: + msr cpsr_c, ip pop {r4, r5, r6, r7, ip, pc} END(__aeabi_cdcmple) @@ -112,6 +113,7 @@ ENTRY(__aeabi_cdcmpeq) RET 1: - msr cpsr_c, #(PCR_C) + mov ip, #(PCR_C) + msr cpsr_c, ip RET END(__aeabi_cdcmpeq) Modified: head/lib/libc/arm/aeabi/aeabi_asm_float.S ============================================================================== --- head/lib/libc/arm/aeabi/aeabi_asm_float.S Sun May 31 08:10:35 2015 (r283806) +++ head/lib/libc/arm/aeabi/aeabi_asm_float.S Sun May 31 09:07:26 2015 (r283807) @@ -54,7 +54,7 @@ ENTRY(__aeabi_cfcmple) cmp r0, #1 bne 1f /* Yes, clear Z and C */ - msr cpsr_c, #(0) + mov ip, #(0) b 99f 1: @@ -66,14 +66,15 @@ ENTRY(__aeabi_cfcmple) cmp r0, #1 bne 2f /* Yes, set Z and C */ - msr cpsr_c, #(PCR_Z | PCR_C) + mov ip, #(PCR_Z | PCR_C) b 99f 2: /* Not less than or equal, set C and clear Z */ - msr cpsr_c, #(PCR_C) + mov ip, #(PCR_C) 99: + msr cpsr_c, ip pop {r4, r5, ip, pc} END(__aeabi_cfcmple) @@ -103,6 +104,7 @@ ENTRY(__aeabi_cfcmpeq) RET 1: - msreq cpsr_c, #(PCR_C) + mov ip, #(PCR_C) + msr cpsr_c, ip RET END(__aeabi_cfcmpeq)