From owner-svn-src-all@FreeBSD.ORG Sat May 23 17:30:32 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D517CD85; Sat, 23 May 2015 17:30:31 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B83651852; Sat, 23 May 2015 17:30:31 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t4NHUVqo082456; Sat, 23 May 2015 17:30:31 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t4NHUVZj082453; Sat, 23 May 2015 17:30:31 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201505231730.t4NHUVZj082453@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sat, 23 May 2015 17:30:30 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r283317 - in stable/10/sys/arm: arm include X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 May 2015 17:30:32 -0000 Author: ian Date: Sat May 23 17:30:30 2015 New Revision: 283317 URL: https://svnweb.freebsd.org/changeset/base/283317 Log: MFC r278770, r279114, r279215, r279338, r279543: Add logic for handling new-style ARM cpu ID info. Correct a comment which was exactly backwards from reality. There is no reason to do i+dcache writeback and invalidate when changing the translation table (this may be left over from armv5 days). It's especially bad to do so using a cache operation that isn't coherent on SMP systems. Add casting to make atomic ops work for pointers. (Apparently nobody has ever done atomic ops on pointers before now on arm). Revert incorrect casting. Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S stable/10/sys/arm/arm/cpuinfo.c stable/10/sys/arm/include/atomic.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- stable/10/sys/arm/arm/cpufunc_asm_armv7.S Sat May 23 16:54:46 2015 (r283316) +++ stable/10/sys/arm/arm/cpufunc_asm_armv7.S Sat May 23 17:30:30 2015 (r283317) @@ -66,11 +66,7 @@ __FBSDID("$FreeBSD$"); #endif ENTRY(armv7_setttb) - stmdb sp!, {r0, lr} - bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ - ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR mcr CP15_TTBR0(r0) isb Modified: stable/10/sys/arm/arm/cpuinfo.c ============================================================================== --- stable/10/sys/arm/arm/cpuinfo.c Sat May 23 16:54:46 2015 (r283316) +++ stable/10/sys/arm/arm/cpuinfo.c Sat May 23 17:30:30 2015 (r283317) @@ -58,9 +58,13 @@ cpuinfo_init(void) /* ARMv4T CPU */ cpuinfo.architecture = 1; cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F; - } + } else { + /* ARM new id scheme */ + cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; + cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; + } } else { - /* must be new id scheme */ + /* non ARM -> must be new id scheme */ cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F; cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F; } Modified: stable/10/sys/arm/include/atomic.h ============================================================================== --- stable/10/sys/arm/include/atomic.h Sat May 23 16:54:46 2015 (r283316) +++ stable/10/sys/arm/include/atomic.h Sat May 23 17:30:30 2015 (r283317) @@ -582,8 +582,8 @@ atomic_load_64(volatile uint64_t *p) /* * The only way to atomically load 64 bits is with LDREXD which puts the - * exclusive monitor into the open state, so reset it with CLREX because - * we don't actually need to store anything. + * exclusive monitor into the exclusive state, so reset it to open state + * with CLREX because we don't actually need to store anything. */ __asm __volatile( "1: \n"