From owner-freebsd-arm@FreeBSD.ORG Thu Jan 13 09:01:33 2011 Return-Path: Delivered-To: arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A9F8E1065670 for ; Thu, 13 Jan 2011 09:01:33 +0000 (UTC) (envelope-from xcllnt@mac.com) Received: from asmtpout029.mac.com (asmtpout029.mac.com [17.148.16.104]) by mx1.freebsd.org (Postfix) with ESMTP id 93E498FC0C for ; Thu, 13 Jan 2011 09:01:33 +0000 (UTC) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=us-ascii Received: from sa-nc-common2-193.static.jnpr.net (natint3.juniper.net [66.129.224.36]) by asmtp029.mac.com (Sun Java(tm) System Messaging Server 6.3-7.04 (built Sep 26 2008; 64bit)) with ESMTPSA id <0LEY003W5BL2HU20@asmtp029.mac.com> for arm@freebsd.org; Thu, 13 Jan 2011 00:00:40 -0800 (PST) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 ipscore=0 suspectscore=1 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx engine=6.0.2-1010190000 definitions=main-1101120222 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.2.15,1.0.148,0.0.0000 definitions=2011-01-13_04:2011-01-13, 2011-01-13, 1970-01-01 signatures=0 From: Marcel Moolenaar Date: Thu, 13 Jan 2011 00:00:38 -0800 Message-id: <5CB52B25-9020-46A4-974A-E4CFAA3DFB30@mac.com> To: arm@freebsd.org X-Mailer: Apple Mail (2.1082) Cc: Subject: Flattened device tree questions X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Jan 2011 09:01:33 -0000 All, I have 2 questions WRT the FDT implementation for ARM: 1. I'm trying to describe a device that has its interrupt through a GPIO pin. This is basically the db88f6281.dts specification, but with an additional on-chip device. Are GPIO based interrupts supported? 2. There's a device in the PCIE bus for which I want to describe the resources. In particular, I want to keep BAR 1 disabled. Also, this device interrupts through a GPIO pin for now. What needs to happen to support this? Thanks, -- Marcel Moolenaar xcllnt@mac.com