From owner-svn-src-all@FreeBSD.ORG Tue Jan 1 04:05:07 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CE007C47; Tue, 1 Jan 2013 04:05:07 +0000 (UTC) (envelope-from andrew@fubar.geek.nz) Received: from smtp-out3.electric.net (smtp-out3.electric.net [72.35.12.187]) by mx1.freebsd.org (Postfix) with ESMTP id A66868FC08; Tue, 1 Jan 2013 04:05:07 +0000 (UTC) Received: from [204.11.168.155] (helo=securemail.onebox.com) by skoda.electric.net with esmtp (Exim 4.77) (envelope-from ) id 1Tpt19-0006fx-Vy; Mon, 31 Dec 2012 19:59:55 -0800 Received: from localhost (unverified [49.226.227.85]) by securemail.onebox.com (Rockliffe SMTPRA 9.3.1) with ESMTP id ; Mon, 31 Dec 2012 22:59:56 -0500 Date: Tue, 1 Jan 2013 16:59:15 +1300 From: Andrew Turner To: Oleksandr Tymoshenko Subject: Re: svn commit: r244914 - in head/sys/arm: arm include ti/omap4 Message-ID: <20130101165915.1f903645@fubar.geek.nz> In-Reply-To: <50E20F2B.7080704@freebsd.org> References: <201212312119.qBVLJi3V009555@svn.freebsd.org> <20130101105353.14492943@fubar.geek.nz> <50E20F2B.7080704@freebsd.org> Organization: SMTP: smtp.paradise.net.nz X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.6; i386-portbld-freebsd8.1) X-Pirate: Arrrr Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Jan 2013 04:05:07 -0000 On Mon, 31 Dec 2012 14:18:19 -0800 Oleksandr Tymoshenko wrote: > On 12/31/2012 1:53 PM, Andrew Turner wrote: > > On Mon, 31 Dec 2012 21:19:44 +0000 (UTC) > > Oleksandr Tymoshenko wrote: > >> Modified: head/sys/arm/arm/pl310.c > >> ============================================================================== > >> --- head/sys/arm/arm/pl310.c Mon Dec 31 21:09:39 2012 > >> (r244913) +++ head/sys/arm/arm/pl310.c Mon Dec 31 21:19:44 > > ... > >> @@ -157,29 +131,46 @@ pl310_wait_background_op(uint32_t off, u > >> static __inline void > >> pl310_cache_sync(void) > >> { > >> - pl310_write4(PL310_CACHE_SYNC, 0); > >> + if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) > >> + return; > >> + > >> +#ifdef PL310_ERRATA_753970 > >> + /* Write uncached PL310 register */ > >> + pl310_write4(pl310_softc, 0x740, 0xffffffff); > >> +#else > >> + pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff); > >> +#endif > >> } > > How hard would it be to detect if we need this errata at boot? From > > the errata document it appears to only be present in the r3p0 > > revision of the controller. We can then do something like: > > > > #ifdef PL310_ERRATA_753970 > > if (errata_753970) > > pl310_write4(pl310_softc, 0x740, 0xffffffff); > > else > > #endif > > pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff); > > > > > > > I think we can use RTL release field of Cache ID register to > determine actual hardware release > and act accordingly. > > Yes, that appears to be correct, I have committed the known values of the RTL release field, from the ARM documentation, in r244919. I can have a look at detecting which cache controller we are on and adjust our behaviour accordingly but won't have any hardware to test with until the end of the week. Andrew