From owner-svn-src-all@freebsd.org Mon Apr 4 17:14:55 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 670A4B0358B; Mon, 4 Apr 2016 17:14:55 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 470851D5D; Mon, 4 Apr 2016 17:14:55 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from ralph.baldwin.cx (c-73-231-226-104.hsd1.ca.comcast.net [73.231.226.104]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 5F729B9A9; Mon, 4 Apr 2016 13:14:54 -0400 (EDT) From: John Baldwin To: Oliver Pinter Cc: "src-committers@freebsd.org" , "svn-src-all@freebsd.org" , "svn-src-head@freebsd.org" Subject: Re: svn commit: r297501 - head/usr.sbin/pciconf Date: Sun, 03 Apr 2016 15:55:54 -0700 Message-ID: <1801560.qVehiR5EY7@ralph.baldwin.cx> User-Agent: KMail/4.14.3 (FreeBSD/10.2-STABLE; KDE/4.14.3; amd64; ; ) In-Reply-To: References: <201604020159.u321xr2V087305@repo.freebsd.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Mon, 04 Apr 2016 13:14:54 -0400 (EDT) X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Apr 2016 17:14:55 -0000 On Saturday, April 02, 2016 11:49:53 AM Oliver Pinter wrote: > > + if (cap & PCIEM_SLOT_CAP_HPS) > > + printf(" surprise"); > > > What is this surprise string or state? Or is this a forgotten debug string? It's an actual thing in the spec. "Surprise" insertion/removal means that devices can be hotplugged without requiring notification to the OS ahead of time. The expresscard slots in my x220 actually report this: pcib3@pci0:0:28:3: class=0x060400 card=0x21da17aa chip=0x1c168086 rev=0xb4 hdr=0x01 cap 10[40] = PCI-Express 2 root port max data 128(128) link x0(x1) speed 0.0(5.0) ASPM L0s/L1(L0s/L1) slot 3 power limit 100 mW HotPlug(empty) surprise cap 05[80] = MSI supports 1 message cap 0d[90] = PCI Bridge card=0x21da17aa cap 01[a0] = powerspec 2 supports D0 D3 current D0 and after inserting a card: pcib3@pci0:0:28:3: class=0x060400 card=0x21da17aa chip=0x1c168086 rev=0xb4 hdr=0x01 cap 10[40] = PCI-Express 2 root port max data 128(128) link x1(x1) speed 2.5(5.0) ASPM disabled(L0s/L1) slot 3 power limit 100 mW HotPlug(present) surprise cap 05[80] = MSI supports 1 message cap 0d[90] = PCI Bridge card=0x21da17aa cap 01[a0] = powerspec 2 supports D0 D3 current D0 -- John Baldwin