From owner-svn-src-stable@FreeBSD.ORG Fri Oct 8 19:39:35 2010 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 52575106566B; Fri, 8 Oct 2010 19:39:35 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 408268FC0C; Fri, 8 Oct 2010 19:39:35 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o98JdZD4011042; Fri, 8 Oct 2010 19:39:35 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o98JdZ7l011039; Fri, 8 Oct 2010 19:39:35 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201010081939.o98JdZ7l011039@svn.freebsd.org> From: Pyun YongHyeon Date: Fri, 8 Oct 2010 19:39:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r213607 - stable/8/sys/dev/sis X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Oct 2010 19:39:35 -0000 Author: yongari Date: Fri Oct 8 19:39:35 2010 New Revision: 213607 URL: http://svn.freebsd.org/changeset/base/213607 Log: MFC r212103-212105: r212103: Remove leading and trailing white spaces. No functional changes. r212104: style(9) - space after keywords. r212105: Nuke unnecessary return at the end of function. Modified: stable/8/sys/dev/sis/if_sis.c stable/8/sys/dev/sis/if_sisreg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/sis/if_sis.c ============================================================================== --- stable/8/sys/dev/sis/if_sis.c Fri Oct 8 19:34:23 2010 (r213606) +++ stable/8/sys/dev/sis/if_sis.c Fri Oct 8 19:39:35 2010 (r213607) @@ -203,7 +203,7 @@ sis_reverse(uint16_t n) n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); - return(n); + return (n); } static void @@ -342,7 +342,7 @@ sis_find_bridge(device_t dev) int i, j; if ((pci_devclass = devclass_find("pci")) == NULL) - return(NULL); + return (NULL); devclass_get_devices(pci_devclass, &pci_devices, &pci_count); @@ -363,7 +363,7 @@ sis_find_bridge(device_t dev) done: free(pci_devices, M_TEMP); - return(child); + return (child); } static void @@ -393,7 +393,6 @@ sis_read_cmos(struct sis_softc *sc, devi } pci_write_config(bridge, 0x48, reg & ~0x40, 1); - return; } static void @@ -406,7 +405,7 @@ sis_read_mac(struct sis_softc *sc, devic CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); CSR_WRITE_4(sc, SIS_CSR, 0); - + CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); @@ -418,7 +417,6 @@ sis_read_mac(struct sis_softc *sc, devic CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); CSR_WRITE_4(sc, SIS_CSR, csrsave); - return; } #endif @@ -429,9 +427,9 @@ static void sis_mii_sync(struct sis_softc *sc) { int i; - + SIO_SET(SIS_MII_DIR|SIS_MII_DATA); - + for (i = 0; i < 32; i++) { SIO_SET(SIS_MII_CLK); DELAY(1); @@ -439,7 +437,7 @@ sis_mii_sync(struct sis_softc *sc) DELAY(1); } } - + /* * Clock a series of bits through the MII. */ @@ -447,9 +445,9 @@ static void sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) { int i; - + SIO_CLR(SIS_MII_CLK); - + for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) { SIO_SET(SIS_MII_DATA); @@ -462,7 +460,7 @@ sis_mii_send(struct sis_softc *sc, uint3 SIO_SET(SIS_MII_CLK); } } - + /* * Read an PHY register through the MII. */ @@ -470,7 +468,7 @@ static int sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) { int i, ack; - + /* * Set up frame for RX. */ @@ -478,14 +476,14 @@ sis_mii_readreg(struct sis_softc *sc, st frame->mii_opcode = SIS_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; - + /* * Turn on data xmit. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); - + /* * Send command/address info. */ @@ -493,29 +491,29 @@ sis_mii_readreg(struct sis_softc *sc, st sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); - + /* Idle bit */ SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); - + /* Turn off xmit. */ SIO_CLR(SIS_MII_DIR); - + /* Check for ack */ SIO_CLR(SIS_MII_CLK); DELAY(1); ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; SIO_SET(SIS_MII_CLK); DELAY(1); - + /* * Now try reading data bits. If the ack failed, we still * need to clock through 16 cycles to keep the PHY(s) in sync. */ if (ack) { - for(i = 0; i < 16; i++) { + for (i = 0; i < 16; i++) { SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); @@ -523,7 +521,7 @@ sis_mii_readreg(struct sis_softc *sc, st } goto fail; } - + for (i = 0x8000; i; i >>= 1) { SIO_CLR(SIS_MII_CLK); DELAY(1); @@ -544,51 +542,51 @@ fail: DELAY(1); if (ack) - return(1); - return(0); + return (1); + return (0); } - + /* * Write to a PHY register through the MII. */ static int sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) { - + /* * Set up frame for TX. */ - + frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_WRITEOP; frame->mii_turnaround = SIS_MII_TURNAROUND; - + /* * Turn on data output. */ SIO_SET(SIS_MII_DIR); - + sis_mii_sync(sc); - + sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); sis_mii_send(sc, frame->mii_turnaround, 2); sis_mii_send(sc, frame->mii_data, 16); - + /* Idle bit. */ SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); - + /* * Turn off xmit. */ SIO_CLR(SIS_MII_DIR); - - return(0); + + return (0); } static int @@ -601,7 +599,7 @@ sis_miibus_readreg(device_t dev, int phy if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) - return(0); + return (0); /* * The NatSemi chip can take a while after * a reset to come ready, during which the BMSR @@ -627,7 +625,7 @@ sis_miibus_readreg(device_t dev, int phy int i, val = 0; if (phy != 0) - return(0); + return (0); CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); @@ -640,15 +638,15 @@ sis_miibus_readreg(device_t dev, int phy if (i == SIS_TIMEOUT) { device_printf(sc->sis_dev, "PHY failed to come ready\n"); - return(0); + return (0); } val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; if (val == 0xFFFF) - return(0); + return (0); - return(val); + return (val); } else { bzero((char *)&frame, sizeof(frame)); @@ -656,7 +654,7 @@ sis_miibus_readreg(device_t dev, int phy frame.mii_regaddr = reg; sis_mii_readreg(sc, &frame); - return(frame.mii_data); + return (frame.mii_data); } } @@ -670,9 +668,9 @@ sis_miibus_writereg(device_t dev, int ph if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) - return(0); + return (0); CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); - return(0); + return (0); } /* @@ -685,7 +683,7 @@ sis_miibus_writereg(device_t dev, int ph int i; if (phy != 0) - return(0); + return (0); CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | (reg << 6) | SIS_PHYOP_WRITE); @@ -706,7 +704,7 @@ sis_miibus_writereg(device_t dev, int ph frame.mii_data = data; sis_mii_writereg(sc, &frame); } - return(0); + return (0); } static void @@ -789,8 +787,6 @@ sis_setmulti_ns(struct sis_softc *sc) if_maddr_runlock(ifp); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); - - return; } static void @@ -876,8 +872,6 @@ sis_reset(struct sis_softc *sc) CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); CSR_WRITE_4(sc, NS_CLKRUN, 0); } - - return; } /* @@ -891,7 +885,7 @@ sis_probe(device_t dev) t = sis_devs; - while(t->sis_name != NULL) { + while (t->sis_name != NULL) { if ((pci_get_vendor(dev) == t->sis_vid) && (pci_get_device(dev) == t->sis_did)) { device_set_desc(dev, t->sis_name); @@ -900,7 +894,7 @@ sis_probe(device_t dev) t++; } - return(ENXIO); + return (ENXIO); } /* @@ -947,8 +941,8 @@ sis_attach(device_t dev) sis_reset(sc); if (sc->sis_type == SIS_TYPE_900 && - (sc->sis_rev == SIS_REV_635 || - sc->sis_rev == SIS_REV_900B)) { + (sc->sis_rev == SIS_REV_635 || + sc->sis_rev == SIS_REV_900B)) { SIO_SET(SIS_CFG_RND_CNT); SIO_SET(SIS_CFG_PERR_DETECT); } @@ -1065,13 +1059,13 @@ sis_attach(device_t dev) * Allocate the parent bus DMA tag appropriate for PCI. */ #define SIS_NSEG_NEW 32 - error = bus_dma_tag_create(NULL, /* parent */ + error = bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ + BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->sis_parent_tag); @@ -1213,7 +1207,7 @@ sis_attach(device_t dev) * Call MI attach routine. */ ether_ifattach(ifp, eaddr); - + /* * Tell the upper layer(s) we support long frames. */ @@ -1238,7 +1232,7 @@ fail: if (error) sis_detach(dev); - return(error); + return (error); } /* @@ -1304,7 +1298,7 @@ sis_detach(device_t dev) mtx_destroy(&sc->sis_mtx); - return(0); + return (0); } /* @@ -1342,7 +1336,7 @@ sis_ring_init(struct sis_softc *sc) for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { error = sis_newbuf(sc, dp, NULL); if (error) - return(error); + return (error); if (i == (SIS_RX_LIST_CNT - 1)) dp->sis_nextdesc = &sc->sis_rx_list[0]; else @@ -1358,7 +1352,7 @@ sis_ring_init(struct sis_softc *sc) sc->sis_rx_pdsc = &sc->sis_rx_list[0]; - return(0); + return (0); } /* @@ -1369,12 +1363,12 @@ sis_newbuf(struct sis_softc *sc, struct { if (c == NULL) - return(EINVAL); + return (EINVAL); if (m == NULL) { m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m == NULL) - return(ENOBUFS); + return (ENOBUFS); } else m->m_data = m->m_ext.ext_buf; @@ -1387,7 +1381,7 @@ sis_newbuf(struct sis_softc *sc, struct sis_dma_map_desc_ptr, c, 0); bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); - return(0); + return (0); } /* @@ -1407,7 +1401,7 @@ sis_rxeof(struct sis_softc *sc) ifp = sc->sis_ifp; - for(cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); + for (cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); cur_rx = cur_rx->sis_nextdesc) { #ifdef DEVICE_POLLING @@ -1444,7 +1438,7 @@ sis_rxeof(struct sis_softc *sc) continue; } - /* No errors; receive the packet. */ + /* No errors; receive the packet. */ #ifdef __NO_STRICT_ALIGNMENT /* * On architectures without alignment problems we try to @@ -1538,8 +1532,6 @@ sis_txeof(struct sis_softc *sc) } sc->sis_watchdog_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; - - return; } static void @@ -1655,7 +1647,7 @@ sis_intr(void *arg) if (status & (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | - SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) + SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) sis_txeof(sc); if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | @@ -1717,7 +1709,7 @@ sis_encap(struct sis_softc *sc, struct m return (ENOBUFS); *m_head = m; } - + /* * Start packing the mbufs in this chain into * the fragment pointers. Stop when we run out @@ -1729,7 +1721,7 @@ sis_encap(struct sis_softc *sc, struct m if (m->m_len != 0) { if ((SIS_TX_LIST_CNT - (sc->sis_tx_cnt + cnt)) < 2) - return(ENOBUFS); + return (ENOBUFS); f = &sc->sis_tx_list[frag]; f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); @@ -1747,7 +1739,7 @@ sis_encap(struct sis_softc *sc, struct m } if (m != NULL) - return(ENOBUFS); + return (ENOBUFS); sc->sis_tx_list[cur].sis_mbuf = *m_head; sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; @@ -1755,7 +1747,7 @@ sis_encap(struct sis_softc *sc, struct m sc->sis_tx_cnt += cnt; *txidx = frag; - return(0); + return (0); } /* @@ -1795,7 +1787,7 @@ sis_startl(struct ifnet *ifp) if (ifp->if_drv_flags & IFF_DRV_OACTIVE) return; - while(sc->sis_tx_list[idx].sis_mbuf == NULL) { + while (sc->sis_tx_list[idx].sis_mbuf == NULL) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; @@ -2003,7 +1995,7 @@ sis_initl(struct sis_softc *sc) uint32_t reg; /* - * Short Cable Receive Errors (MP21.E) + * Short Cable Receive Errors (MP21.E) */ CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; @@ -2071,7 +2063,7 @@ sis_ifmedia_upd(struct ifnet *ifp) mii_mediachg(mii); SIS_UNLOCK(sc); - return(0); + return (0); } /* @@ -2101,7 +2093,7 @@ sis_ioctl(struct ifnet *ifp, u_long comm struct mii_data *mii; int error = 0; - switch(command) { + switch (command) { case SIOCSIFFLAGS: SIS_LOCK(sc); if (ifp->if_flags & IFF_UP) { @@ -2134,14 +2126,14 @@ sis_ioctl(struct ifnet *ifp, u_long comm !(ifp->if_capenable & IFCAP_POLLING)) { error = ether_poll_register(sis_poll, ifp); if (error) - return(error); + return (error); SIS_LOCK(sc); /* Disable interrupts */ CSR_WRITE_4(sc, SIS_IER, 0); ifp->if_capenable |= IFCAP_POLLING; SIS_UNLOCK(sc); return (error); - + } if (!(ifr->ifr_reqcap & IFCAP_POLLING) && ifp->if_capenable & IFCAP_POLLING) { @@ -2160,7 +2152,7 @@ sis_ioctl(struct ifnet *ifp, u_long comm break; } - return(error); + return (error); } static void Modified: stable/8/sys/dev/sis/if_sisreg.h ============================================================================== --- stable/8/sys/dev/sis/if_sisreg.h Fri Oct 8 19:34:23 2010 (r213606) +++ stable/8/sys/dev/sis/if_sisreg.h Fri Oct 8 19:39:35 2010 (r213607) @@ -252,7 +252,7 @@ SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ -#define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */ +#define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */ #define SIS_RXCFG_DMABURST 0x00700000 #define SIS_RXCFG_RX_JABBER 0x08000000 #define SIS_RXCFG_RX_TXPKTS 0x10000000