From owner-cvs-src@FreeBSD.ORG Tue Oct 18 15:54:43 2005 Return-Path: X-Original-To: cvs-src@freebsd.org Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id DFC5516A41F; Tue, 18 Oct 2005 15:54:43 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from duke.cs.duke.edu (duke.cs.duke.edu [152.3.140.1]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6E1EE43D45; Tue, 18 Oct 2005 15:54:43 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from grasshopper.cs.duke.edu (grasshopper.cs.duke.edu [152.3.145.30]) by duke.cs.duke.edu (8.13.4/8.13.4) with ESMTP id j9IFsgQ7003688 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 18 Oct 2005 11:54:42 -0400 (EDT) Received: (from gallatin@localhost) by grasshopper.cs.duke.edu (8.12.9p2/8.12.9/Submit) id j9IFsbtQ030042; Tue, 18 Oct 2005 11:54:37 -0400 (EDT) (envelope-from gallatin) From: Andrew Gallatin MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17237.6845.390864.858367@grasshopper.cs.duke.edu> Date: Tue, 18 Oct 2005 11:54:37 -0400 (EDT) To: John Baldwin In-Reply-To: <200510181101.03956.jhb@freebsd.org> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <20051018094402.A29138@grasshopper.cs.duke.edu> <200510181101.03956.jhb@freebsd.org> X-Mailer: VM 6.75 under 21.1 (patch 12) "Channel Islands" XEmacs Lucid Cc: cvs-src@freebsd.org, src-committers@freebsd.org, David Xu , cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Oct 2005 15:54:44 -0000 John Baldwin writes: > On Tuesday 18 October 2005 09:44 am, Andrew Gallatin wrote: > > David Xu [davidxu@FreeBSD.org] wrote: > > > davidxu 2005-10-17 23:10:31 UTC > > > > > > FreeBSD src repository > > > > > > Modified files: > > > sys/amd64/amd64 cpu_switch.S machdep.c > > > Log: > > > Micro optimization for context switch. Eliminate code for saving > > > gs.base and fs.base. We always update pcb.pcb_gsbase and pcb.pcb_fsbase > > > when user wants to set them, in context switch routine, we only need to > > > write them into registers, we never have to read them out from registers > > > when thread is switched away. Since rdmsr is a serialization instruction, > > > micro benchmark shows it is worthy to do. > > > > Nice. This reduces lmbench context switch latency by about 0.4us (7.2 > > -> 6.8us), and reduces TCP loopback latency by about 0.9us (36.1 -> > > 35.2) on my dual core 3800+ > > > > It is a shame we can't find a way to use the TSC as a timecounter on > > SMP systems. It seems that about 40% of the context switch time is > > spent just waiting for the PIO read of the ACPI-fast or i8254 to > > return. > > You can try it by just setting the kern.timecounter.smp_tsc=1 tunable on boot. Yes, that's how I get my figure of 3us for PIO read, and 3.8us for the rest of the context switch. But its not currently practical on most machines, since we don't sync the TSC between cpus, or do anything to account for drift. Drew