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From: Peter Grehan <grehan@FreeBSD.org>
Date: Wed, 4 Feb 2004 05:10:26 -0800 (PST)
To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org,
	cvs-all@FreeBSD.org
X-FreeBSD-CVS-Branch: HEAD
Subject: cvs commit: src/sys/powerpc/powerpc trap_subr.S
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grehan      2004/02/04 05:10:26 PST

  FreeBSD src repository

  Modified files:
    sys/powerpc/powerpc  trap_subr.S 
  Log:
  Major overhaul of common trap code
   - remove unused 601 and tlb exception code
   - remove interrupt-time PTE spill code. The pmap code
     will now take care of pinning kernel PTEs, and there
     are no longer issues about physical mapping of PTE
     data structures
   - All segment registers are switched on kernel entry/exit,
     allowing the kernel to have more virtual space and for
     user virtual space to extend to 4G.
   - The temporary register save area has been shifted from
     unused exception vector space to the per-cpu data area.
     This allows interrupts to be delivered to multiple CPUs
   - ISI traps no longer spill to BAT tables. It is assumed
     that all of kernel instruction memory is pinned.
   - shift from 'ldmw/stmw' instructions to individual register
     loads/stores when saving context. All PPC manuals indicate
     this should be much faster.
   - use '%r' for register names throughout.
  
  TODO: need to test if DSI traps were the result of kernel stack
  guard-page hits.
  
  Reworked from:  NetBSD
  
  Revision  Changes    Path
  1.10      +359 -812  src/sys/powerpc/powerpc/trap_subr.S