From owner-p4-projects@FreeBSD.ORG Tue Sep 26 15:31:03 2006 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1B8B316A59F; Tue, 26 Sep 2006 15:31:03 +0000 (UTC) X-Original-To: perforce@FreeBSD.org Delivered-To: perforce@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E7B1A16A58C for ; Tue, 26 Sep 2006 15:31:02 +0000 (UTC) (envelope-from attilio@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 7BEBE43D5C for ; Tue, 26 Sep 2006 15:30:33 +0000 (GMT) (envelope-from attilio@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.6/8.13.6) with ESMTP id k8QFUXZ9040684 for ; Tue, 26 Sep 2006 15:30:33 GMT (envelope-from attilio@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.6/8.13.4/Submit) id k8QFUX0M040681 for perforce@freebsd.org; Tue, 26 Sep 2006 15:30:33 GMT (envelope-from attilio@FreeBSD.org) Date: Tue, 26 Sep 2006 15:30:33 GMT Message-Id: <200609261530.k8QFUX0M040681@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to attilio@FreeBSD.org using -f From: Attilio Rao To: Perforce Change Reviews Cc: Subject: PERFORCE change 106725 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Sep 2006 15:31:03 -0000 http://perforce.freebsd.org/chv.cgi?CH=106725 Change 106725 by attilio@attilio_laptop on 2006/09/26 15:30:18 Style-ize them Affected files ... .. //depot/projects/usb/src/sys/dev/usb/if_udavreg.h#6 edit .. //depot/projects/usb/src/sys/dev/usb/if_uralreg.h#6 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb/if_udavreg.h#6 (text+ko) ==== @@ -34,7 +34,7 @@ #define UDAV_IFACE_INDEX 0 #define UDAV_CONFIG_NO 1 -#define UDAV_ENDPT_MAX 6 /* units */ +#define UDAV_ENDPT_MAX 6 /* units */ /* Packet length */ #define UDAV_MIN_FRAME_LEN 60 @@ -50,49 +50,49 @@ /* Registers */ #define UDAV_NCR 0x00 /* Network Control Register */ -#define UDAV_NCR_EXT_PHY (1<<7) /* Select External PHY */ -#define UDAV_NCR_WAKEEN (1<<6) /* Wakeup Event Enable */ -#define UDAV_NCR_FCOL (1<<4) /* Force Collision Mode */ -#define UDAV_NCR_FDX (1<<3) /* Full-Duplex Mode (RO on Int. PHY) */ -#define UDAV_NCR_LBK1 (1<<2) /* Lookback Mode */ -#define UDAV_NCR_LBK0 (1<<1) /* Lookback Mode */ -#define UDAV_NCR_RST (1<<0) /* Software reset */ +#define UDAV_NCR_EXT_PHY (1<<7) /* Select External PHY */ +#define UDAV_NCR_WAKEEN (1<<6) /* Wakeup Event Enable */ +#define UDAV_NCR_FCOL (1<<4) /* Force Collision Mode */ +#define UDAV_NCR_FDX (1<<3) /* Full-Duplex Mode (RO on Int. PHY) */ +#define UDAV_NCR_LBK1 (1<<2) /* Lookback Mode */ +#define UDAV_NCR_LBK0 (1<<1) /* Lookback Mode */ +#define UDAV_NCR_RST (1<<0) /* Software reset */ #define UDAV_RCR 0x05 /* RX Control Register */ -#define UDAV_RCR_WTDIS (1<<6) /* Watchdog Timer Disable */ -#define UDAV_RCR_DIS_LONG (1<<5) /* Discard Long Packet(over 1522Byte) */ -#define UDAV_RCR_DIS_CRC (1<<4) /* Discard CRC Error Packet */ -#define UDAV_RCR_ALL (1<<3) /* Pass All Multicast */ -#define UDAV_RCR_RUNT (1<<2) /* Pass Runt Packet */ -#define UDAV_RCR_PRMSC (1<<1) /* Promiscuous Mode */ -#define UDAV_RCR_RXEN (1<<0) /* RX Enable */ +#define UDAV_RCR_WTDIS (1<<6) /* Watchdog Timer Disable */ +#define UDAV_RCR_DIS_LONG (1<<5) /* Discard Long Packet(over 1522Byte) */ +#define UDAV_RCR_DIS_CRC (1<<4) /* Discard CRC Error Packet */ +#define UDAV_RCR_ALL (1<<3) /* Pass All Multicast */ +#define UDAV_RCR_RUNT (1<<2) /* Pass Runt Packet */ +#define UDAV_RCR_PRMSC (1<<1) /* Promiscuous Mode */ +#define UDAV_RCR_RXEN (1<<0) /* RX Enable */ #define UDAV_RSR 0x06 /* RX Status Register */ -#define UDAV_RSR_RF (1<<7) /* Runt Frame */ -#define UDAV_RSR_MF (1<<6) /* Multicast Frame */ -#define UDAV_RSR_LCS (1<<5) /* Late Collision Seen */ -#define UDAV_RSR_RWTO (1<<4) /* Receive Watchdog Time-Out */ -#define UDAV_RSR_PLE (1<<3) /* Physical Layer Error */ -#define UDAV_RSR_AE (1<<2) /* Alignment Error */ -#define UDAV_RSR_CE (1<<1) /* CRC Error */ -#define UDAV_RSR_FOE (1<<0) /* FIFO Overflow Error */ -#define UDAV_RSR_ERR (UDAV_RSR_RF | UDAV_RSR_LCS | UDAV_RSR_RWTO |\ - UDAV_RSR_PLE | UDAV_RSR_AE | UDAV_RSR_CE |\ - UDAV_RSR_FOE) +#define UDAV_RSR_RF (1<<7) /* Runt Frame */ +#define UDAV_RSR_MF (1<<6) /* Multicast Frame */ +#define UDAV_RSR_LCS (1<<5) /* Late Collision Seen */ +#define UDAV_RSR_RWTO (1<<4) /* Receive Watchdog Time-Out */ +#define UDAV_RSR_PLE (1<<3) /* Physical Layer Error */ +#define UDAV_RSR_AE (1<<2) /* Alignment Error */ +#define UDAV_RSR_CE (1<<1) /* CRC Error */ +#define UDAV_RSR_FOE (1<<0) /* FIFO Overflow Error */ +#define UDAV_RSR_ERR (UDAV_RSR_RF | UDAV_RSR_LCS | \ + UDAV_RSR_RWTO | UDAV_RSR_PLE | \ + UDAV_RSR_AE | UDAV_RSR_CE | UDAV_RSR_FOE) #define UDAV_EPCR 0x0b /* EEPROM & PHY Control Register */ -#define UDAV_EPCR_REEP (1<<5) /* Reload EEPROM */ -#define UDAV_EPCR_WEP (1<<4) /* Write EEPROM enable */ -#define UDAV_EPCR_EPOS (1<<3) /* EEPROM or PHY Operation Select */ -#define UDAV_EPCR_ERPRR (1<<2) /* EEPROM/PHY Register Read Command */ -#define UDAV_EPCR_ERPRW (1<<1) /* EEPROM/PHY Register Write Command */ -#define UDAV_EPCR_ERRE (1<<0) /* EEPROM/PHY Access Status */ +#define UDAV_EPCR_REEP (1<<5) /* Reload EEPROM */ +#define UDAV_EPCR_WEP (1<<4) /* Write EEPROM enable */ +#define UDAV_EPCR_EPOS (1<<3) /* EEPROM or PHY Operation Select */ +#define UDAV_EPCR_ERPRR (1<<2) /* EEPROM/PHY Register Read Command */ +#define UDAV_EPCR_ERPRW (1<<1) /* EEPROM/PHY Register Write Command */ +#define UDAV_EPCR_ERRE (1<<0) /* EEPROM/PHY Access Status */ #define UDAV_EPAR 0x0c /* EEPROM & PHY Control Register */ -#define UDAV_EPAR_PHY_ADR1 (1<<7) /* PHY Address bit 1 */ -#define UDAV_EPAR_PHY_ADR0 (1<<6) /* PHY Address bit 0 */ -#define UDAV_EPAR_EROA (1<<0) /* EEPROM Word/PHY Register Address */ -#define UDAV_EPAR_EROA_MASK (0x1f) /* [5:0] */ +#define UDAV_EPAR_PHY_ADR1 (1<<7) /* PHY Address bit 1 */ +#define UDAV_EPAR_PHY_ADR0 (1<<6) /* PHY Address bit 0 */ +#define UDAV_EPAR_EROA (1<<0) /* EEPROM Word/PHY Register Address */ +#define UDAV_EPAR_EROA_MASK (0x1f) /* [5:0] */ #define UDAV_EPDRL 0x0d /* EEPROM & PHY Data Register */ #define UDAV_EPDRH 0x0e /* EEPROM & PHY Data Register */ @@ -116,25 +116,25 @@ #define UDAV_MAR UDAV_MAR0 #define UDAV_GPCR 0x1e /* General purpose control register */ -#define UDAV_GPCR_GEP_CNTL6 (1<<6) /* General purpose control 6 */ -#define UDAV_GPCR_GEP_CNTL5 (1<<5) /* General purpose control 5 */ -#define UDAV_GPCR_GEP_CNTL4 (1<<4) /* General purpose control 4 */ -#define UDAV_GPCR_GEP_CNTL3 (1<<3) /* General purpose control 3 */ -#define UDAV_GPCR_GEP_CNTL2 (1<<2) /* General purpose control 2 */ -#define UDAV_GPCR_GEP_CNTL1 (1<<1) /* General purpose control 1 */ -#define UDAV_GPCR_GEP_CNTL0 (1<<0) /* General purpose control 0 */ +#define UDAV_GPCR_GEP_CNTL6 (1<<6) /* General purpose control 6 */ +#define UDAV_GPCR_GEP_CNTL5 (1<<5) /* General purpose control 5 */ +#define UDAV_GPCR_GEP_CNTL4 (1<<4) /* General purpose control 4 */ +#define UDAV_GPCR_GEP_CNTL3 (1<<3) /* General purpose control 3 */ +#define UDAV_GPCR_GEP_CNTL2 (1<<2) /* General purpose control 2 */ +#define UDAV_GPCR_GEP_CNTL1 (1<<1) /* General purpose control 1 */ +#define UDAV_GPCR_GEP_CNTL0 (1<<0) /* General purpose control 0 */ #define UDAV_GPR 0x1f /* General purpose register */ -#define UDAV_GPR_GEPIO6 (1<<6) /* General purpose 6 */ -#define UDAV_GPR_GEPIO5 (1<<5) /* General purpose 5 */ -#define UDAV_GPR_GEPIO4 (1<<4) /* General purpose 4 */ -#define UDAV_GPR_GEPIO3 (1<<3) /* General purpose 3 */ -#define UDAV_GPR_GEPIO2 (1<<2) /* General purpose 2 */ -#define UDAV_GPR_GEPIO1 (1<<1) /* General purpose 1 */ -#define UDAV_GPR_GEPIO0 (1<<0) /* General purpose 0 */ +#define UDAV_GPR_GEPIO6 (1<<6) /* General purpose 6 */ +#define UDAV_GPR_GEPIO5 (1<<5) /* General purpose 5 */ +#define UDAV_GPR_GEPIO4 (1<<4) /* General purpose 4 */ +#define UDAV_GPR_GEPIO3 (1<<3) /* General purpose 3 */ +#define UDAV_GPR_GEPIO2 (1<<2) /* General purpose 2 */ +#define UDAV_GPR_GEPIO1 (1<<1) /* General purpose 1 */ +#define UDAV_GPR_GEPIO0 (1<<0) /* General purpose 0 */ -#define GET_MII(sc) ((sc)->sc_miibus ? \ - device_get_softc((sc)->sc_miibus) : NULL) +#define GET_MII(sc) ((sc)->sc_miibus ? \ + device_get_softc((sc)->sc_miibus) : NULL) struct udav_softc { struct usbd_config_td sc_config_td; @@ -148,24 +148,24 @@ device_t sc_miibus; device_t sc_dev; - u_int32_t sc_unit; - u_int32_t sc_media_active; - u_int32_t sc_media_status; + uint32_t sc_unit; + uint32_t sc_media_active; + uint32_t sc_media_status; - u_int16_t sc_flags; -#define UDAV_FLAG_WAIT_LINK 0x0001 -#define UDAV_FLAG_INTR_STALL 0x0002 -#define UDAV_FLAG_READ_STALL 0x0004 -#define UDAV_FLAG_WRITE_STALL 0x0008 -#define UDAV_FLAG_LL_READY 0x0010 -#define UDAV_FLAG_HL_READY 0x0020 -#define UDAV_FLAG_EXT_PHY 0x0040 + uint16_t sc_flags; +#define UDAV_FLAG_WAIT_LINK 0x0001 +#define UDAV_FLAG_INTR_STALL 0x0002 +#define UDAV_FLAG_READ_STALL 0x0004 +#define UDAV_FLAG_WRITE_STALL 0x0008 +#define UDAV_FLAG_LL_READY 0x0010 +#define UDAV_FLAG_HL_READY 0x0020 +#define UDAV_FLAG_EXT_PHY 0x0040 - u_int8_t sc_name[16]; + uint8_t sc_name[16]; }; struct udav_config_copy { - u_int32_t if_flags; - u_int8_t if_lladdr[ETHER_ADDR_LEN]; - u_int8_t if_hashes[8]; + uint32_t if_flags; + uint8_t if_lladdr[ETHER_ADDR_LEN]; + uint8_t if_hashes[8]; }; ==== //depot/projects/usb/src/sys/dev/usb/if_uralreg.h#6 (text+ko) ==== @@ -17,191 +17,174 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) -#define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) +#define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) +#define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) -#define RAL_CONFIG_NO 1 -#define RAL_IFACE_INDEX 0 +#define RAL_CONFIG_NO 1 +#define RAL_IFACE_INDEX 0 -#define RAL_VENDOR_REQUEST 0x01 -#define RAL_WRITE_MAC 0x02 -#define RAL_READ_MAC 0x03 -#define RAL_WRITE_MULTI_MAC 0x06 -#define RAL_READ_MULTI_MAC 0x07 -#define RAL_READ_EEPROM 0x09 +#define RAL_VENDOR_REQUEST 0x01 +#define RAL_WRITE_MAC 0x02 +#define RAL_READ_MAC 0x03 +#define RAL_WRITE_MULTI_MAC 0x06 +#define RAL_READ_MULTI_MAC 0x07 +#define RAL_READ_EEPROM 0x09 -/* - * MAC registers. - */ -#define RAL_MAC_CSR0 0x0400 /* ASIC Version */ -#define RAL_MAC_CSR1 0x0402 /* System control */ -#define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ -#define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ -#define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ -#define RAL_MAC_CSR5 0x040a /* BSSID0 */ -#define RAL_MAC_CSR6 0x040c /* BSSID1 */ -#define RAL_MAC_CSR7 0x040e /* BSSID2 */ -#define RAL_MAC_CSR8 0x0410 /* Max frame length */ -#define RAL_MAC_CSR9 0x0412 /* Timer control */ -#define RAL_MAC_CSR10 0x0414 /* Slot time */ -#define RAL_MAC_CSR11 0x0416 /* IFS */ -#define RAL_MAC_CSR12 0x0418 /* EIFS */ -#define RAL_MAC_CSR13 0x041a /* Power mode0 */ -#define RAL_MAC_CSR14 0x041c /* Power mode1 */ -#define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ -#define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ -#define RAL_MAC_CSR17 0x0422 /* Power state control */ -#define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ -#define RAL_MAC_CSR19 0x0426 /* GPIO control */ -#define RAL_MAC_CSR20 0x0428 /* LED control0 */ -#define RAL_MAC_CSR22 0x042c /* XXX not documented */ +/* MAC registers. */ +#define RAL_MAC_CSR0 0x0400 /* ASIC Version */ +#define RAL_MAC_CSR1 0x0402 /* System control */ +#define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ +#define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ +#define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ +#define RAL_MAC_CSR5 0x040a /* BSSID0 */ +#define RAL_MAC_CSR6 0x040c /* BSSID1 */ +#define RAL_MAC_CSR7 0x040e /* BSSID2 */ +#define RAL_MAC_CSR8 0x0410 /* Max frame length */ +#define RAL_MAC_CSR9 0x0412 /* Timer control */ +#define RAL_MAC_CSR10 0x0414 /* Slot time */ +#define RAL_MAC_CSR11 0x0416 /* IFS */ +#define RAL_MAC_CSR12 0x0418 /* EIFS */ +#define RAL_MAC_CSR13 0x041a /* Power mode0 */ +#define RAL_MAC_CSR14 0x041c /* Power mode1 */ +#define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ +#define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ +#define RAL_MAC_CSR17 0x0422 /* Power state control */ +#define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ +#define RAL_MAC_CSR19 0x0426 /* GPIO control */ +#define RAL_MAC_CSR20 0x0428 /* LED control0 */ +#define RAL_MAC_CSR22 0x042c /* XXX not documented */ -/* - * Tx/Rx Registers. - */ -#define RAL_TXRX_CSR0 0x0440 /* Security control */ -#define RAL_TXRX_CSR2 0x0444 /* Rx control */ -#define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ -#define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ -#define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ -#define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ -#define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ -#define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ -#define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ -#define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ -#define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ -#define RAL_TXRX_CSR21 0x046a /* XXX not documented */ +/* Tx/Rx Registers. */ +#define RAL_TXRX_CSR0 0x0440 /* Security control */ +#define RAL_TXRX_CSR2 0x0444 /* Rx control */ +#define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ +#define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ +#define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ +#define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ +#define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ +#define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ +#define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ +#define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ +#define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ +#define RAL_TXRX_CSR21 0x046a /* XXX not documented */ -/* - * Security registers. - */ -#define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ +/* Security registers. */ +#define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ -/* - * PHY registers. - */ -#define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ -#define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ -#define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ -#define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ -#define RAL_PHY_CSR7 0x04ce /* BBP serial control */ -#define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ -#define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ -#define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ +/* PHY registers. */ +#define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ +#define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ +#define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ +#define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ +#define RAL_PHY_CSR7 0x04ce /* BBP serial control */ +#define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ +#define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ +#define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ -/* - * Statistics registers. - */ -#define RAL_STA_CSR0 0x04e0 /* FCS error */ +/* Statistics registers. */ +#define RAL_STA_CSR0 0x04e0 /* FCS error */ +#define RAL_DISABLE_RX (1 << 0) +#define RAL_DROP_CRC (1 << 1) +#define RAL_DROP_PHY (1 << 2) +#define RAL_DROP_CTL (1 << 3) +#define RAL_DROP_NOT_TO_ME (1 << 4) +#define RAL_DROP_TODS (1 << 5) +#define RAL_DROP_BAD_VERSION (1 << 6) +#define RAL_DROP_MULTICAST (1 << 9) +#define RAL_DROP_BROADCAST (1 << 10) -#define RAL_DISABLE_RX (1 << 0) -#define RAL_DROP_CRC (1 << 1) -#define RAL_DROP_PHY (1 << 2) -#define RAL_DROP_CTL (1 << 3) -#define RAL_DROP_NOT_TO_ME (1 << 4) -#define RAL_DROP_TODS (1 << 5) -#define RAL_DROP_BAD_VERSION (1 << 6) -#define RAL_DROP_MULTICAST (1 << 9) -#define RAL_DROP_BROADCAST (1 << 10) +#define RAL_SHORT_PREAMBLE (1 << 2) -#define RAL_SHORT_PREAMBLE (1 << 2) +#define RAL_RESET_ASIC (1 << 0) +#define RAL_RESET_BBP (1 << 1) +#define RAL_HOST_READY (1 << 2) -#define RAL_RESET_ASIC (1 << 0) -#define RAL_RESET_BBP (1 << 1) -#define RAL_HOST_READY (1 << 2) +#define RAL_ENABLE_TSF (1 << 0) +#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) +#define RAL_ENABLE_TBCN (1 << 3) +#define RAL_ENABLE_BEACON_GENERATOR (1 << 4) -#define RAL_ENABLE_TSF (1 << 0) -#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) -#define RAL_ENABLE_TBCN (1 << 3) -#define RAL_ENABLE_BEACON_GENERATOR (1 << 4) +#define RAL_RF_AWAKE (3 << 7) +#define RAL_BBP_AWAKE (3 << 5) -#define RAL_RF_AWAKE (3 << 7) -#define RAL_BBP_AWAKE (3 << 5) +#define RAL_BBP_WRITE (1 << 15) +#define RAL_BBP_BUSY (1 << 0) -#define RAL_BBP_WRITE (1 << 15) -#define RAL_BBP_BUSY (1 << 0) +#define RAL_RF1_AUTOTUNE 0x08000 +#define RAL_RF3_AUTOTUNE 0x00040 -#define RAL_RF1_AUTOTUNE 0x08000 -#define RAL_RF3_AUTOTUNE 0x00040 - -#define RAL_RF_2522 0x00 -#define RAL_RF_2523 0x01 -#define RAL_RF_2524 0x02 -#define RAL_RF_2525 0x03 -#define RAL_RF_2525E 0x04 -#define RAL_RF_2526 0x05 +#define RAL_RF_2522 0x00 +#define RAL_RF_2523 0x01 +#define RAL_RF_2524 0x02 +#define RAL_RF_2525 0x03 +#define RAL_RF_2525E 0x04 +#define RAL_RF_2526 0x05 /* dual-band RF */ -#define RAL_RF_5222 0x10 +#define RAL_RF_5222 0x10 -#define RAL_BBP_VERSION 0 -#define RAL_BBP_TX 2 -#define RAL_BBP_RX 14 +#define RAL_BBP_VERSION 0 +#define RAL_BBP_TX 2 +#define RAL_BBP_RX 14 -#define RAL_BBP_ANTA 0x00 -#define RAL_BBP_DIVERSITY 0x01 -#define RAL_BBP_ANTB 0x02 -#define RAL_BBP_ANTMASK 0x03 -#define RAL_BBP_FLIPIQ 0x04 +#define RAL_BBP_ANTA 0x00 +#define RAL_BBP_DIVERSITY 0x01 +#define RAL_BBP_ANTB 0x02 +#define RAL_BBP_ANTMASK 0x03 +#define RAL_BBP_FLIPIQ 0x04 -#define RAL_JAPAN_FILTER 0x08 +#define RAL_JAPAN_FILTER 0x08 -struct ural_tx_desc { - u_int32_t flags; -#define RAL_TX_RETRY(x) ((x) << 4) -#define RAL_TX_MORE_FRAG (1 << 8) -#define RAL_TX_ACK (1 << 9) -#define RAL_TX_TIMESTAMP (1 << 10) -#define RAL_TX_OFDM (1 << 11) -#define RAL_TX_NEWSEQ (1 << 12) +#define RAL_RF_LOBUSY (1 << 15) +#define RAL_RF_BUSY (1 << 31) +#define RAL_RF_20BIT (20 << 24) -#define RAL_TX_IFS_MASK 0x00006000 -#define RAL_TX_IFS_BACKOFF (0 << 13) -#define RAL_TX_IFS_SIFS (1 << 13) -#define RAL_TX_IFS_NEWBACKOFF (2 << 13) -#define RAL_TX_IFS_NONE (3 << 13) +#define RAL_RF1 0 +#define RAL_RF2 2 +#define RAL_RF3 1 +#define RAL_RF4 3 - u_int16_t wme; -#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) -#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) -#define RAL_AIFSN(x) (((x) & 0x3) << 6) -#define RAL_IVOFFSET(x) (((x) & 0x3f)) +#define RAL_EEPROM_ADDRESS 0x0004 +#define RAL_EEPROM_TXPOWER 0x003c +#define RAL_EEPROM_CONFIG0 0x0016 +#define RAL_EEPROM_BBP_BASE 0x001c - u_int16_t reserved1; - u_int8_t plcp_signal; - u_int8_t plcp_service; -#define RAL_PLCP_LENGEXT 0x80 - - u_int8_t plcp_length_lo; - u_int8_t plcp_length_hi; - u_int32_t iv; - u_int32_t eiv; +struct ural_tx_desc { + uint32_t flags; +#define RAL_TX_RETRY(x) ((x) << 4) +#define RAL_TX_MORE_FRAG (1 << 8) +#define RAL_TX_ACK (1 << 9) +#define RAL_TX_TIMESTAMP (1 << 10) +#define RAL_TX_OFDM (1 << 11) +#define RAL_TX_NEWSEQ (1 << 12) +#define RAL_TX_IFS_MASK 0x00006000 +#define RAL_TX_IFS_BACKOFF (0 << 13) +#define RAL_TX_IFS_SIFS (1 << 13) +#define RAL_TX_IFS_NEWBACKOFF (2 << 13) +#define RAL_TX_IFS_NONE (3 << 13) + uint16_t wme; +#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) +#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) +#define RAL_AIFSN(x) (((x) & 0x3) << 6) +#define RAL_IVOFFSET(x) (((x) & 0x3f)) + uint16_t reserved1; + uint8_t plcp_signal; + uint8_t plcp_service; +#define RAL_PLCP_LENGEXT 0x80 + uint8_t plcp_length_lo; + uint8_t plcp_length_hi; + uint32_t iv; + uint32_t eiv; } __packed; struct ural_rx_desc { - u_int32_t flags; -#define RAL_RX_CRC_ERROR (1 << 5) -#define RAL_RX_OFDM (1 << 6) -#define RAL_RX_PHY_ERROR (1 << 7) - - u_int8_t rssi; - u_int8_t rate; - u_int16_t reserved; - - u_int32_t iv; - u_int32_t eiv; + uint32_t flags; +#define RAL_RX_CRC_ERROR (1 << 5) +#define RAL_RX_OFDM (1 << 6) +#define RAL_RX_PHY_ERROR (1 << 7) + uint8_t rssi; + uint8_t rate; + uint16_t reserved; + uint32_t iv; + uint32_t eiv; } __packed; - -#define RAL_RF_LOBUSY (1 << 15) -#define RAL_RF_BUSY (1 << 31) -#define RAL_RF_20BIT (20 << 24) - -#define RAL_RF1 0 -#define RAL_RF2 2 -#define RAL_RF3 1 -#define RAL_RF4 3 - -#define RAL_EEPROM_ADDRESS 0x0004 -#define RAL_EEPROM_TXPOWER 0x003c -#define RAL_EEPROM_CONFIG0 0x0016 -#define RAL_EEPROM_BBP_BASE 0x001c