From owner-p4-projects@FreeBSD.ORG Thu Oct 30 10:17:49 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C554B16A4D0; Thu, 30 Oct 2003 10:17:48 -0800 (PST) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A07D916A4CE for ; Thu, 30 Oct 2003 10:17:48 -0800 (PST) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 08B0643FAF for ; Thu, 30 Oct 2003 10:17:48 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.9/8.12.9) with ESMTP id h9UIHlXJ055511 for ; Thu, 30 Oct 2003 10:17:47 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.9/8.12.9/Submit) id h9UIHl7F055508 for perforce@freebsd.org; Thu, 30 Oct 2003 10:17:47 -0800 (PST) (envelope-from jmallett@freebsd.org) Date: Thu, 30 Oct 2003 10:17:47 -0800 (PST) Message-Id: <200310301817.h9UIHl7F055508@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 40846 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Oct 2003 18:17:49 -0000 http://perforce.freebsd.org/chv.cgi?CH=40846 Change 40846 by jmallett@jmallett_sprout on 2003/10/30 10:16:59 Kill SUPPORT_SB1 and CCA-related bits. Affected files ... .. //depot/projects/mips/sys/mips/include/cpu.h#12 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#33 edit Differences ... ==== //depot/projects/mips/sys/mips/include/cpu.h#12 (text+ko) ==== @@ -128,9 +128,6 @@ #define CPU_MIPS_R4K_MMU 0x0001 #define CPU_MIPS_NO_LLSC 0x0002 #define CPU_MIPS_CAUSE_IV 0x0004 -#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ -#define CPU_MIPS_CACHED_CCA_MASK 0x0070 -#define CPU_MIPS_CACHED_CCA_SHIFT 4 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ ==== //depot/projects/mips/sys/mips/mips/machdep.c#33 (text+ko) ==== @@ -173,9 +173,6 @@ int mips_cpu_flags; int mips_has_r4k_mmu; int mips_has_llsc; -#ifdef SUPPORT_SB1 -int mips3_pg_cached; -#endif int mips_num_tlb_entries; @@ -532,14 +529,6 @@ MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, "Au1100 (Rev 2 core)" }, -#ifdef SUPPORT_SB1 - /* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */ - { MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0, - MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | - CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), - "SB1" }, -#endif /* SUPPORT_SB1 */ - { 0, 0, 0, 0, 0, 0, 0, NULL } }; @@ -715,17 +704,6 @@ mips_has_r4k_mmu = mips_cpu_flags & CPU_MIPS_R4K_MMU; mips_has_llsc = (mips_cpu_flags & CPU_MIPS_NO_LLSC) == 0; -#ifdef SUPPORT_SB1 - if (mycpu->cpu_flags & CPU_MIPS_HAVE_SPECIAL_CCA) { - uint32_t cca; - - cca = (ct->cpu_flags & CPU_MIPS_CACHED_CCA_MASK) >> - CPU_MIPS_CACHED_CCA_SHIFT; - mips3_pg_cached = MIPS3_CCA_TO_PG(cca); - } else - mips3_pg_cached = MIPS3_DEFAULT_PG_CACHED; -#endif SUPPORT_SB1 - #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG mips_machdep_cache_config(); #endif