From owner-svn-src-stable@FreeBSD.ORG Fri Nov 16 07:07:01 2012 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 67F5FAB9; Fri, 16 Nov 2012 07:07:01 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 4C4D68FC08; Fri, 16 Nov 2012 07:07:01 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qAG7710w037522; Fri, 16 Nov 2012 07:07:01 GMT (envelope-from kib@svn.freebsd.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qAG771v6037518; Fri, 16 Nov 2012 07:07:01 GMT (envelope-from kib@svn.freebsd.org) Message-Id: <201211160707.qAG771v6037518@svn.freebsd.org> From: Konstantin Belousov Date: Fri, 16 Nov 2012 07:07:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r243139 - in stable/9/sys/amd64: amd64 include X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2012 07:07:01 -0000 Author: kib Date: Fri Nov 16 07:07:00 2012 New Revision: 243139 URL: http://svnweb.freebsd.org/changeset/base/243139 Log: MFC r242432: Provide the reading and display of the Standard Extended Features, introduced with the IvyBridge CPUs. Provide the definitions for new bits in CR3 and CR4 registers. Modified: stable/9/sys/amd64/amd64/identcpu.c stable/9/sys/amd64/amd64/initcpu.c stable/9/sys/amd64/include/md_var.h stable/9/sys/amd64/include/specialreg.h Directory Properties: stable/9/sys/ (props changed) Modified: stable/9/sys/amd64/amd64/identcpu.c ============================================================================== --- stable/9/sys/amd64/amd64/identcpu.c Fri Nov 16 07:05:57 2012 (r243138) +++ stable/9/sys/amd64/amd64/identcpu.c Fri Nov 16 07:07:00 2012 (r243139) @@ -384,6 +384,18 @@ printcpuinfo(void) ); } + if (cpu_stdext_feature != 0) { + printf("\n Standard Extended Features=0x%b", + cpu_stdext_feature, + "\020" + "\001GSFSBASE" + "\002TSCADJ" + "\010SMEP" + "\012ENHMOVSB" + "\013INVPCID" + ); + } + if (via_feature_rng != 0 || via_feature_xcrypt != 0) print_via_padlock_info(); @@ -501,6 +513,11 @@ identify_cpu(void) } } + if (cpu_high >= 7) { + cpuid_count(7, 0, regs); + cpu_stdext_feature = regs[1]; + } + if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD || cpu_vendor_id == CPU_VENDOR_CENTAUR) { Modified: stable/9/sys/amd64/amd64/initcpu.c ============================================================================== --- stable/9/sys/amd64/amd64/initcpu.c Fri Nov 16 07:05:57 2012 (r243138) +++ stable/9/sys/amd64/amd64/initcpu.c Fri Nov 16 07:07:00 2012 (r243139) @@ -72,6 +72,7 @@ u_int cpu_vendor_id; /* CPU vendor ID * u_int cpu_fxsr; /* SSE enabled */ u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ u_int cpu_clflush_line_size = 32; +u_int cpu_stdext_feature; u_int cpu_max_ext_state_size; SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, Modified: stable/9/sys/amd64/include/md_var.h ============================================================================== --- stable/9/sys/amd64/include/md_var.h Fri Nov 16 07:05:57 2012 (r243138) +++ stable/9/sys/amd64/include/md_var.h Fri Nov 16 07:07:00 2012 (r243139) @@ -48,6 +48,7 @@ extern u_int amd_pminfo; extern u_int via_feature_rng; extern u_int via_feature_xcrypt; extern u_int cpu_clflush_line_size; +extern u_int cpu_stdext_feature; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id; Modified: stable/9/sys/amd64/include/specialreg.h ============================================================================== --- stable/9/sys/amd64/include/specialreg.h Fri Nov 16 07:05:57 2012 (r243138) +++ stable/9/sys/amd64/include/specialreg.h Fri Nov 16 07:07:00 2012 (r243139) @@ -52,6 +52,8 @@ #define CR0_NW 0x20000000 /* Not Write-through */ #define CR0_CD 0x40000000 /* Cache Disable */ +#define CR3_PCID_SAVE 0x8000000000000000 + /* * Bits in PPro special registers */ @@ -66,7 +68,10 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ +#define CR4_PCIDE 0x00020000 /* Enable Context ID */ #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ +#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. @@ -261,6 +266,12 @@ #define AMDID_COREID_SIZE 0x0000f000 #define AMDID_COREID_SIZE_SHIFT 12 +#define CPUID_STDEXT_FSGSBASE 0x00000001 +#define CPUID_STDEXT_TSC_ADJUST 0x00000002 +#define CPUID_STDEXT_SMEP 0x00000080 +#define CPUID_STDEXT_ENH_MOVSB 0x00000200 +#define CPUID_STDEXT_INVPCID 0x00000400 + /* * CPUID manufacturers identifiers */