From owner-freebsd-arch@FreeBSD.ORG Mon Apr 13 15:29:03 2009 Return-Path: Delivered-To: arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C3712106568C; Mon, 13 Apr 2009 15:29:03 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from cyrus.watson.org (cyrus.watson.org [65.122.17.42]) by mx1.freebsd.org (Postfix) with ESMTP id 812228FC24; Mon, 13 Apr 2009 15:29:03 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (66.111.2.69.static.nyinternet.net [66.111.2.69]) by cyrus.watson.org (Postfix) with ESMTPSA id 7C64E46B35; Mon, 13 Apr 2009 11:29:02 -0400 (EDT) Received: from jhbbsd.hudson-trading.com (unknown [209.249.190.8]) by bigwig.baldwin.cx (Postfix) with ESMTPA id 198E08A04F; Mon, 13 Apr 2009 11:28:43 -0400 (EDT) From: John Baldwin To: freebsd-arch@freebsd.org Date: Mon, 13 Apr 2009 10:22:53 -0400 User-Agent: KMail/1.9.7 References: <49E0D353.7090308@freebsd.org> In-Reply-To: <49E0D353.7090308@freebsd.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200904131022.53882.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (bigwig.baldwin.cx); Mon, 13 Apr 2009 11:28:43 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.95 at bigwig.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=0.1 required=4.2 tests=RDNS_NONE autolearn=no version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on bigwig.baldwin.cx Cc: arch@freebsd.org, Robert Watson , Nathan Whitehorn Subject: Re: Simple #define for cache line size X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Apr 2009 15:29:04 -0000 On Saturday 11 April 2009 1:28:51 pm Nathan Whitehorn wrote: > Robert Watson wrote: > > > > > > NetBSD, FYI, defines CACHE_LINE_SIZE as a global constant in param.h, > > but I'm going with an MD definition as I suspect people will want to > > do different things on different architectures (and there is > > variation). I've defaulted all architectures to 64 bytes, but I > > suspect a number would prefer to use 32. > For what it's worth, this is per-CPU variable on PowerPC and detected at > runtime. Most of the CPUs we support have 32 byte cache lines, but some > (e.g. the G5) use 128 bytes. I'm not sure there is a general solution in > this case, but that's the situation on PPC. > -Nathan I think UMA can handle a variable size and that should be preserved. However, for the purposes of aligned() I think a constant that is the maximum size (such as 128 on ppc) might work best. -- John Baldwin