From owner-cvs-src@FreeBSD.ORG Wed Mar 1 16:50:24 2006 Return-Path: X-Original-To: cvs-src@FreeBSD.org Delivered-To: cvs-src@FreeBSD.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 6BB2C16A420; Wed, 1 Mar 2006 16:50:24 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from duke.cs.duke.edu (duke.cs.duke.edu [152.3.140.1]) by mx1.FreeBSD.org (Postfix) with ESMTP id 4BA9A43D77; Wed, 1 Mar 2006 16:50:23 +0000 (GMT) (envelope-from gallatin@cs.duke.edu) Received: from grasshopper.cs.duke.edu (grasshopper.cs.duke.edu [152.3.145.30]) by duke.cs.duke.edu (8.13.4/8.13.4) with ESMTP id k21GoLKd012676 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 1 Mar 2006 11:50:22 -0500 (EST) Received: (from gallatin@localhost) by grasshopper.cs.duke.edu (8.12.9p2/8.12.9/Submit) id k21GoGtx008443; Wed, 1 Mar 2006 11:50:16 -0500 (EST) (envelope-from gallatin) From: Andrew Gallatin MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <17413.53448.389083.210260@grasshopper.cs.duke.edu> Date: Wed, 1 Mar 2006 11:50:16 -0500 (EST) To: Scott Long In-Reply-To: <4405CF88.4040904@samsco.org> References: <200602282224.k1SMOtJt070241@repoman.freebsd.org> <200602281735.12240.jhb@freebsd.org> <4404D37E.9040502@samsco.org> <20060301113803.A8330@grasshopper.cs.duke.edu> <4405CF88.4040904@samsco.org> X-Mailer: VM 6.75 under 21.1 (patch 12) "Channel Islands" XEmacs Lucid Cc: cvs-src@FreeBSD.org, src-committers@FreeBSD.org, cvs-all@FreeBSD.org, John Baldwin Subject: Re: cvs commit: src/sys/amd64/amd64 intr_machdep.c io_apic.c local_apic.c mp_machdep.c src/sys/amd64/include apicvar.h intr_machdep.h src/sys/amd64/isa atpic.c src/sys/i386/i386 intr_machdep.c io_apic.c local_apic.c mp_machdep.c ... X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Mar 2006 16:50:24 -0000 Scott Long writes: > Andrew Gallatin wrote: > > > Scott Long [scottl@samsco.org] wrote: > > <...> > > > >> Also, it's not so > >>much important which CPU gets the interrupt as it is which CPU runs the > >>ithread for that interrupt. I guess that you can get a little better > >>latency by preempting directly from the low-level interrupt handler into > >>the ithread, but I don't know if that is noticable noise above the cost > >>of the context switch and inevitable lock operations and contention > >>involved. > > > > > > What do you mean by "preempting directly from the low-level interrupt > > handler into the ithread" ? Do you mean running the ithread directly > > in the context of the hardware interrupt until it does something where > > it needed to block? Do we do this now? > > > > Thanks, > > > > Drew > > > > > > No, I just mean that the CPU running the low-level handler is likely > to schedule and run the ithread as soon as the interrupt exits, > preempting whatever thread happened to be running before the interrupt > occurred. This isn't context stealing, it's just preferential > scheduling. You still need to wind through the scheduler and do a > context switch to get there. Oh, darn. Nevermind :) Drew