From owner-freebsd-current@FreeBSD.ORG Tue Jan 10 21:40:02 2012 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 52E9D1065675 for ; Tue, 10 Jan 2012 21:40:02 +0000 (UTC) (envelope-from freebsd@damnhippie.dyndns.org) Received: from qmta06.emeryville.ca.mail.comcast.net (qmta06.emeryville.ca.mail.comcast.net [76.96.30.56]) by mx1.freebsd.org (Postfix) with ESMTP id 389DB8FC15 for ; Tue, 10 Jan 2012 21:40:01 +0000 (UTC) Received: from omta07.emeryville.ca.mail.comcast.net ([76.96.30.59]) by qmta06.emeryville.ca.mail.comcast.net with comcast id Kxfx1i0011GXsucA6xg1Yi; Tue, 10 Jan 2012 21:40:01 +0000 Received: from damnhippie.dyndns.org ([24.8.232.202]) by omta07.emeryville.ca.mail.comcast.net with comcast id Kxfz1i00M4NgCEG8Uxg0q0; Tue, 10 Jan 2012 21:40:01 +0000 Received: from [172.22.42.240] (revolution.hippie.lan [172.22.42.240]) by damnhippie.dyndns.org (8.14.3/8.14.3) with ESMTP id q0ALdvS1026796; Tue, 10 Jan 2012 14:39:57 -0700 (MST) (envelope-from freebsd@damnhippie.dyndns.org) From: Ian Lepore To: Luigi Rizzo In-Reply-To: <20120110213719.GA92799@onelab2.iet.unipi.it> References: <20120110213719.GA92799@onelab2.iet.unipi.it> Content-Type: text/plain Date: Tue, 10 Jan 2012 14:39:57 -0700 Message-Id: <1326231597.2419.46.camel@revolution.hippie.lan> Mime-Version: 1.0 X-Mailer: Evolution 2.26.0 FreeBSD GNOME Team Port Content-Transfer-Encoding: 7bit Cc: FreeBSD current Subject: Re: memory barriers in bus_dmamap_sync() ? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2012 21:40:02 -0000 On Tue, 2012-01-10 at 22:37 +0100, Luigi Rizzo wrote: > I was glancing through manpages and implementations of bus_dma(9) > and i am a bit unclear on what this API (in particular, bus_dmamap_sync() ) > does in terms of memory barriers. > > I see that the x86/amd64 and ia64 code only does the bounce buffers. > The mips seems to do some coherency-related calls. > > How do we guarantee, say, that a recently built packet is > to memory before issuing the tx command to the NIC ? > > cheers > luigi I've always assumed that when the concept of a memory barrier means anything for a given architecture, it's implied that the bus_dmamap_sync() call has to invoke it as needed to ensure the DMA operation picks up the right data. Maybe it would be good if the manpage said that straight out. The ARM implementations do use the memory barrier operations, in the form of a call to cpu_drain_writebuf() in the busdma_machdep code. The ARM specification says that the CPU is stopped until all buffered data is written to memory for that operation. -- Ian