From owner-freebsd-i386@FreeBSD.ORG Wed Feb 6 15:57:06 2008 Return-Path: Delivered-To: freebsd-i386@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 226C216A421 for ; Wed, 6 Feb 2008 15:57:06 +0000 (UTC) (envelope-from obw@amarok.ping.de) Received: from lilly.ping.de (lilly.ping.de [83.97.42.2]) by mx1.freebsd.org (Postfix) with SMTP id 80DDF13C46A for ; Wed, 6 Feb 2008 15:57:05 +0000 (UTC) (envelope-from obw@amarok.ping.de) Received: (qmail 2116 invoked by uid 10); 6 Feb 2008 15:57:03 -0000 Received: from amarok.ping.de by lilly.ping.de with UUCP (rmail-0.2-fdc); 6 Feb 2008 15:57:03 -0000 Received: from karnevil9.amarok.ping.de (localhost [127.0.0.1]) by karnevil9.amarok.ping.de (8.13.8/8.13.8) with ESMTP id m16FtEKZ004900; Wed, 6 Feb 2008 16:55:15 +0100 (CET) (envelope-from obw@karnevil9.amarok.ping.de) Received: (from obw@localhost) by karnevil9.amarok.ping.de (8.13.8/8.13.8/Submit) id m16FtE6V004899; Wed, 6 Feb 2008 16:55:14 +0100 (CET) (envelope-from obw) Date: Wed, 6 Feb 2008 16:55:14 +0100 From: "Oliver B. Warzecha" To: Bruce Evans Message-ID: <20080206155514.GD1361@karnevil9.amarok.ping.de> References: <200801112032.m0BKWFXg001186@karnevil9.amarok.ping.de> <20080113225917.Y50887@delplex.bde.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080113225917.Y50887@delplex.bde.org> User-Agent: Mutt/1.4.2.3i X-message-flag: Please send plain text messages only. Thank you. Cc: FreeBSD-gnats-submit@FreeBSD.ORG, freebsd-i386@FreeBSD.ORG Subject: Re: i386/119574: 7.0-RC1 times out in calibrate_clocks() X-BeenThere: freebsd-i386@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: I386-specific issues for FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Feb 2008 15:57:06 -0000 Addon to my last mail, as I just discovered the i440BX-Specs, just 2 clicks away from one of the pages where I last searched for info. They are downloadable from http://www.intel.com/design/intarch/datashts/290562.htm On page 84, there is specified that the RTC index register is write only (as I found out in practical testing :-). And it is also described as a latch register, which makes the current code "working by pure chance", as it's implementation dependent which bus noise happens on the other side of the gate. (If I didn't get the meaning of "latch" in this case totally wrong) regards, OBW