From owner-freebsd-embedded@FreeBSD.ORG Tue Dec 13 10:03:19 2011 Return-Path: Delivered-To: freebsd-embedded@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BA1D0106564A; Tue, 13 Dec 2011 10:03:19 +0000 (UTC) (envelope-from stb@lassitu.de) Received: from gilb.zs64.net (gilb.zs64.net [IPv6:2001:470:1f0b:105e::1ea]) by mx1.freebsd.org (Postfix) with ESMTP id 769758FC12; Tue, 13 Dec 2011 10:03:19 +0000 (UTC) Received: by gilb.zs64.net (Postfix, from stb@lassitu.de) id A718C5767A; Tue, 13 Dec 2011 11:03:18 +0100 (CET) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Stefan Bethke In-Reply-To: Date: Tue, 13 Dec 2011 11:03:17 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: References: <68ABED76-CB1F-405A-8036-EC254F7511FA@lassitu.de> <3B3DB17D-BF87-40EE-B1C1-445F178E8844@lassitu.de> <86030CEE-6839-4B96-ACDC-2BA9AC1E4AE4@lassitu.de> <2D625CC9-A0E3-47AA-A504-CE8FB2F90245@lassitu.de> <203BF1C8-D528-40C9-8611-9C7AC7E43BAB@lassitu.de> <3C0E9CA3-E130-4E9A-ABCC-1782E28999D1@lassitu.de> <6387ABA5-AC55-49DD-9058-E45CC0A3E0A0@lassitu.de> <74E4AF57-3D22-415E-B913-176753B09B16@lassitu.de> <710E2C7A-E9AC-4103-8C61-0EDC4A3AF9DE@lassitu.de> To: Adrian Chadd X-Mailer: Apple Mail (2.1084) Cc: freebsd-embedded@freebsd.org Subject: Re: TL-WR1043: switch X-BeenThere: freebsd-embedded@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Dedicated and Embedded Systems List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Dec 2011 10:03:19 -0000 Am 13.12.2011 um 11:02 schrieb Adrian Chadd: > On 12 December 2011 23:54, Stefan Bethke wrote: >>> Does the arge0 "phy" map to a specific switch port phy, for general >>> configuration and status? Or is it totally separate here (requiring >>> configuration of rtl8366rb0portX ?) >>=20 >> There is no PHY connected to arge0, just the switch MAC. I believe = the RTL8366RB configures the CPU port (port 5) through pin strapping on = power up. My code only return the current configuration, but does not = allow you to change it. >=20 > Ok. So what's arge0's PHY configuration coming from? Or is it being > handled as a multi-phy, where it forces speed/duplex (and MAC PLL + > MII clock but I have to fix that for ar71xx/ar724x) and then just > nails the port as always up, rather than binding a phy instance to it? It's hard-wired on both ends, the PHY MAC and the arge MAC. Stefan --=20 Stefan Bethke Fon +49 151 14070811