From owner-svn-src-all@FreeBSD.ORG Sun Dec 22 20:40:56 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id BB6A6E1F; Sun, 22 Dec 2013 20:40:56 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 9B916177A; Sun, 22 Dec 2013 20:40:56 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rBMKeuOu021019; Sun, 22 Dec 2013 20:40:56 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.7/8.14.7/Submit) id rBMKeuch021018; Sun, 22 Dec 2013 20:40:56 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201312222040.rBMKeuch021018@svn.freebsd.org> From: Ian Lepore Date: Sun, 22 Dec 2013 20:40:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r259739 - head/sys/arm/ti/am335x X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 Dec 2013 20:40:56 -0000 Author: ian Date: Sun Dec 22 20:40:56 2013 New Revision: 259739 URL: http://svnweb.freebsd.org/changeset/base/259739 Log: Shorten the DMTIMER_ prefix used for register names to DMT_. This is in preparation for adding more complete register defintions, some of which have fairly long names. Modified: head/sys/arm/ti/am335x/am335x_dmtimer.c Modified: head/sys/arm/ti/am335x/am335x_dmtimer.c ============================================================================== --- head/sys/arm/ti/am335x/am335x_dmtimer.c Sun Dec 22 20:31:40 2013 (r259738) +++ head/sys/arm/ti/am335x/am335x_dmtimer.c Sun Dec 22 20:40:56 2013 (r259739) @@ -53,23 +53,23 @@ __FBSDID("$FreeBSD$"); #define AM335X_NUM_TIMERS 8 -#define DMTIMER_TIDR 0x00 /* Identification Register */ -#define DMTIMER_TIOCP_CFG 0x10 /* Timer OCP Configuration Reg */ -#define DMTIMER_IQR_EOI 0x20 /* Timer IRQ End-Of-Interrupt Reg */ -#define DMTIMER_IRQSTATUS_RAW 0x24 /* Timer IRQSTATUS Raw Reg */ -#define DMTIMER_IRQSTATUS 0x28 /* Timer IRQSTATUS Reg */ -#define DMTIMER_IRQENABLE_SET 0x2c /* Timer IRQSTATUS Set Reg */ -#define DMTIMER_IRQENABLE_CLR 0x30 /* Timer IRQSTATUS Clear Reg */ -#define DMTIMER_IRQWAKEEN 0x34 /* Timer IRQ Wakeup Enable Reg */ -#define DMTIMER_TCLR 0x38 /* Timer Control Register */ -#define DMTIMER_TCRR 0x3C /* Timer Counter Register */ -#define DMTIMER_TLDR 0x40 /* Timer Load Reg */ -#define DMTIMER_TTGR 0x44 /* Timer Trigger Reg */ -#define DMTIMER_TWPS 0x48 /* Timer Write Posted Status Reg */ -#define DMTIMER_TMAR 0x4C /* Timer Match Reg */ -#define DMTIMER_TCAR1 0x50 /* Timer Capture Reg */ -#define DMTIMER_TSICR 0x54 /* Timer Synchr. Interface Control Reg */ -#define DMTIMER_TCAR2 0x48 /* Timer Capture Reg */ +#define DMT_TIDR 0x00 /* Identification Register */ +#define DMT_TIOCP_CFG 0x10 /* Timer OCP Configuration Reg */ +#define DMT_IQR_EOI 0x20 /* Timer IRQ End-Of-Interrupt Reg */ +#define DMT_IRQSTATUS_RAW 0x24 /* Timer IRQSTATUS Raw Reg */ +#define DMT_IRQSTATUS 0x28 /* Timer IRQSTATUS Reg */ +#define DMT_IRQENABLE_SET 0x2c /* Timer IRQSTATUS Set Reg */ +#define DMT_IRQENABLE_CLR 0x30 /* Timer IRQSTATUS Clear Reg */ +#define DMT_IRQWAKEEN 0x34 /* Timer IRQ Wakeup Enable Reg */ +#define DMT_TCLR 0x38 /* Timer Control Register */ +#define DMT_TCRR 0x3C /* Timer Counter Register */ +#define DMT_TLDR 0x40 /* Timer Load Reg */ +#define DMT_TTGR 0x44 /* Timer Trigger Reg */ +#define DMT_TWPS 0x48 /* Timer Write Posted Status Reg */ +#define DMT_TMAR 0x4C /* Timer Match Reg */ +#define DMT_TCAR1 0x50 /* Timer Capture Reg */ +#define DMT_TSICR 0x54 /* Timer Synchr. Interface Control Reg */ +#define DMT_TCAR2 0x48 /* Timer Capture Reg */ struct am335x_dmtimer_softc { @@ -138,7 +138,7 @@ static struct timecounter am335x_dmtimer static unsigned am335x_dmtimer_tc_get_timecount(struct timecounter *tc) { - return am335x_dmtimer_tc_read_4(DMTIMER_TCRR); + return am335x_dmtimer_tc_read_4(DMT_TCRR); } static int @@ -162,23 +162,23 @@ am335x_dmtimer_start(struct eventtimer * count = load; /* Reset Timer */ - am335x_dmtimer_et_write_4(DMTIMER_TSICR, 2); + am335x_dmtimer_et_write_4(DMT_TSICR, 2); /* Wait for reset to complete */ - while (am335x_dmtimer_et_read_4(DMTIMER_TIOCP_CFG) & 1); + while (am335x_dmtimer_et_read_4(DMT_TIOCP_CFG) & 1); /* set load value */ - am335x_dmtimer_et_write_4(DMTIMER_TLDR, 0xFFFFFFFE - load); + am335x_dmtimer_et_write_4(DMT_TLDR, 0xFFFFFFFE - load); /* set counter value */ - am335x_dmtimer_et_write_4(DMTIMER_TCRR, 0xFFFFFFFE - count); + am335x_dmtimer_et_write_4(DMT_TCRR, 0xFFFFFFFE - count); /* enable overflow interrupt */ - am335x_dmtimer_et_write_4(DMTIMER_IRQENABLE_SET, 2); + am335x_dmtimer_et_write_4(DMT_IRQENABLE_SET, 2); /* start timer(ST) */ tclr |= 1; - am335x_dmtimer_et_write_4(DMTIMER_TCLR, tclr); + am335x_dmtimer_et_write_4(DMT_TCLR, tclr); return (0); } @@ -189,10 +189,10 @@ am335x_dmtimer_stop(struct eventtimer *e struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)et->et_priv; /* Disable all interrupts */ - am335x_dmtimer_et_write_4(DMTIMER_IRQENABLE_CLR, 7); + am335x_dmtimer_et_write_4(DMT_IRQENABLE_CLR, 7); /* Stop Timer */ - am335x_dmtimer_et_write_4(DMTIMER_TCLR, 0); + am335x_dmtimer_et_write_4(DMT_TCLR, 0); return (0); } @@ -203,7 +203,7 @@ am335x_dmtimer_intr(void *arg) struct am335x_dmtimer *tmr = (struct am335x_dmtimer *)arg; /* Ack interrupt */ - am335x_dmtimer_et_write_4(DMTIMER_IRQSTATUS, 7); + am335x_dmtimer_et_write_4(DMT_IRQSTATUS, 7); if (tmr->et.et_active) tmr->et.et_event_cb(&tmr->et, tmr->et.et_arg); @@ -277,19 +277,19 @@ am335x_dmtimer_attach(device_t dev) am335x_dmtimer_tc_tmr = &sc->t[2]; /* Reset Timer */ - am335x_dmtimer_tc_write_4(DMTIMER_TSICR, 2); + am335x_dmtimer_tc_write_4(DMT_TSICR, 2); /* Wait for reset to complete */ - while (am335x_dmtimer_tc_read_4(DMTIMER_TIOCP_CFG) & 1); + while (am335x_dmtimer_tc_read_4(DMT_TIOCP_CFG) & 1); /* set load value */ - am335x_dmtimer_tc_write_4(DMTIMER_TLDR, 0); + am335x_dmtimer_tc_write_4(DMT_TLDR, 0); /* set counter value */ - am335x_dmtimer_tc_write_4(DMTIMER_TCRR, 0); + am335x_dmtimer_tc_write_4(DMT_TCRR, 0); /* Set Timer autoreload(AR) and start timer(ST) */ - am335x_dmtimer_tc_write_4(DMTIMER_TCLR, 3); + am335x_dmtimer_tc_write_4(DMT_TCLR, 3); am335x_dmtimer_tc.tc_frequency = sc->sysclk_freq; tc_init(&am335x_dmtimer_tc); @@ -361,10 +361,10 @@ DELAY(int usec) /* Get the number of times to count */ counts = usec * (am335x_dmtimer_tc.tc_frequency / 1000000) + 1; - first = am335x_dmtimer_tc_read_4(DMTIMER_TCRR); + first = am335x_dmtimer_tc_read_4(DMT_TCRR); while (counts > 0) { - last = am335x_dmtimer_tc_read_4(DMTIMER_TCRR); + last = am335x_dmtimer_tc_read_4(DMT_TCRR); if (last>first) { counts -= (int32_t)(last - first); } else {