From owner-svn-src-user@FreeBSD.ORG Sun Apr 18 22:02:56 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 20AFE1065670; Sun, 18 Apr 2010 22:02:56 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 0FD6C8FC1B; Sun, 18 Apr 2010 22:02:56 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3IM2txd006527; Sun, 18 Apr 2010 22:02:55 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3IM2tld006523; Sun, 18 Apr 2010 22:02:55 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201004182202.o3IM2tld006523@svn.freebsd.org> From: Juli Mallett Date: Sun, 18 Apr 2010 22:02:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r206816 - in user/jmallett/octeon/sys/mips: include mips X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 18 Apr 2010 22:02:56 -0000 Author: jmallett Date: Sun Apr 18 22:02:55 2010 New Revision: 206816 URL: http://svn.freebsd.org/changeset/base/206816 Log: Add support for showing a remote CPU's TLB entries back. Modified: user/jmallett/octeon/sys/mips/include/tlb.h user/jmallett/octeon/sys/mips/mips/mp_machdep.c user/jmallett/octeon/sys/mips/mips/tlb.c Modified: user/jmallett/octeon/sys/mips/include/tlb.h ============================================================================== --- user/jmallett/octeon/sys/mips/include/tlb.h Sun Apr 18 21:36:34 2010 (r206815) +++ user/jmallett/octeon/sys/mips/include/tlb.h Sun Apr 18 22:02:55 2010 (r206816) @@ -33,6 +33,7 @@ void tlb_insert_wired(unsigned, vm_offse void tlb_invalidate_address(struct pmap *, vm_offset_t); void tlb_invalidate_all(void); void tlb_invalidate_all_user(struct pmap *); +void tlb_save(void); void tlb_update(struct pmap *, vm_offset_t, pt_entry_t); #endif /* !_MACHINE_TLB_H_ */ Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/mp_machdep.c Sun Apr 18 21:36:34 2010 (r206815) +++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c Sun Apr 18 22:02:55 2010 (r206816) @@ -129,6 +129,7 @@ mips_ipi_handler(void *arg) CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); savectx(&stoppcbs[cpu]); + tlb_save(); /* Indicate we are stopped */ atomic_set_int(&stopped_cpus, cpumask); Modified: user/jmallett/octeon/sys/mips/mips/tlb.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/tlb.c Sun Apr 18 21:36:34 2010 (r206815) +++ user/jmallett/octeon/sys/mips/mips/tlb.c Sun Apr 18 22:02:55 2010 (r206816) @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,17 @@ #include #include +struct tlb_state { + unsigned wired; + struct tlb_entry { + register_t entryhi; + register_t entrylo0; + register_t entrylo1; + } entry[MIPS_MAX_TLB_ENTRIES]; +}; + +static struct tlb_state tlb_state[MAXCPU]; + #if 0 /* * PageMask must increment in steps of 2 bits. @@ -183,6 +195,25 @@ tlb_invalidate_all_user(struct pmap *pma intr_restore(s); } +/* XXX Only if DDB? */ +void +tlb_save(void) +{ + unsigned i, cpu; + + cpu = PCPU_GET(cpuid); + + tlb_state[cpu].wired = mips_rd_wired(); + for (i = 0; i < num_tlbentries; i++) { + mips_wr_index(i); + tlb_read(); + + tlb_state[cpu].entry[i].entryhi = mips_rd_entryhi(); + tlb_state[cpu].entry[i].entrylo0 = mips_rd_entrylo0(); + tlb_state[cpu].entry[i].entrylo1 = mips_rd_entrylo1(); + } +} + void tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte) { @@ -235,22 +266,38 @@ tlb_invalidate_one(unsigned i) DB_SHOW_COMMAND(tlb, ddb_dump_tlb) { register_t ehi, elo0, elo1; - unsigned i; + unsigned i, cpu; - db_printf("Beginning TLB dump...\n"); + /* + * XXX + * The worst conversion from hex to decimal ever. + */ + if (have_addr) + cpu = ((addr >> 4) % 16) * 10 + (addr % 16); + else + cpu = PCPU_GET(cpuid); + + if (cpu < 0 || cpu >= mp_ncpus) { + db_printf("Invalid CPU %u\n", cpu); + return; + } + + if (cpu == PCPU_GET(cpuid)) + tlb_save(); + + db_printf("Beginning TLB dump for CPU %u...\n", cpu); for (i = 0; i < num_tlbentries; i++) { - if (i == mips_rd_wired()) { + if (i == tlb_state[cpu].wired) { if (i != 0) db_printf("^^^ WIRED ENTRIES ^^^\n"); else db_printf("(No wired entries.)\n"); } - mips_wr_index(i); - tlb_read(); - ehi = mips_rd_entryhi(); - elo0 = mips_rd_entrylo0(); - elo1 = mips_rd_entrylo1(); + /* XXX PageMask. */ + ehi = tlb_state[cpu].entry[i].entryhi; + elo0 = tlb_state[cpu].entry[i].entrylo0; + elo1 = tlb_state[cpu].entry[i].entrylo1; if (elo0 == 0 && elo1 == 0) continue;