From owner-svn-src-all@FreeBSD.ORG Sat Jul 2 12:56:03 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BBD03106564A; Sat, 2 Jul 2011 12:56:03 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 9265C8FC13; Sat, 2 Jul 2011 12:56:03 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p62Cu3aj040539; Sat, 2 Jul 2011 12:56:03 GMT (envelope-from marius@svn.freebsd.org) Received: (from marius@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p62Cu3Yp040536; Sat, 2 Jul 2011 12:56:03 GMT (envelope-from marius@svn.freebsd.org) Message-Id: <201107021256.p62Cu3Yp040536@svn.freebsd.org> From: Marius Strobl Date: Sat, 2 Jul 2011 12:56:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r223721 - head/sys/sparc64/sparc64 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Jul 2011 12:56:03 -0000 Author: marius Date: Sat Jul 2 12:56:03 2011 New Revision: 223721 URL: http://svn.freebsd.org/changeset/base/223721 Log: UltraSPARC-IV CPUs seem to be affected by a not publicly documented erratum causing them to trigger stray vector interrupts accompanied by a state in which they even fault on locked TLB entries. Just retrying the instruction in that case gets the CPU back on track though. OpenSolaris also just ignores a certain number of stray vector interrupts. While at it, implement the stray vector interrupt handling for SPARC64-VI which use these for indicating uncorrectable errors in interrupt packets. Modified: head/sys/sparc64/sparc64/exception.S head/sys/sparc64/sparc64/interrupt.S Modified: head/sys/sparc64/sparc64/exception.S ============================================================================== --- head/sys/sparc64/sparc64/exception.S Sat Jul 2 11:46:23 2011 (r223720) +++ head/sys/sparc64/sparc64/exception.S Sat Jul 2 12:56:03 2011 (r223721) @@ -585,7 +585,8 @@ END(tl0_sfsr_trap) andcc %g1, IRSR_BUSY, %g0 bnz,a,pt %xcc, intr_vector nop - sir + ba,a,pt %xcc, intr_vector_stray + nop .align 32 .endm Modified: head/sys/sparc64/sparc64/interrupt.S ============================================================================== --- head/sys/sparc64/sparc64/interrupt.S Sat Jul 2 11:46:23 2011 (r223720) +++ head/sys/sparc64/sparc64/interrupt.S Sat Jul 2 12:56:03 2011 (r223721) @@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include "assym.s" @@ -153,6 +154,29 @@ ENTRY(intr_vector) retry END(intr_vector) +ENTRY(intr_vector_stray) + /* + * SPARC64-VI trigger stray vector interrupts in order to indicate + * uncorrectable errors in interrupt packets, which still need to be + * acknowledged though. + * US-IV occasionally trigger stray vector interrupts for reasons + * unknown accompanied by a state in which they even fault on locked + * TLB entries so we can't even log these here. Just retrying the + * instruction in that case gets the CPU back on track. + */ + rdpr %ver, %g1 + srlx %g1, VER_IMPL_SHIFT, %g1 + sll %g1, VER_IMPL_SIZE, %g1 + srl %g1, VER_IMPL_SIZE, %g1 + cmp %g1, CPU_IMPL_SPARC64VI + bne,a,pn %icc, 1f + nop + stxa %g0, [%g0] ASI_INTR_RECEIVE + membar #Sync + +1: retry +END(intr_vector_stray) + ENTRY(intr_fast) save %sp, -CCFSZ, %sp