From owner-svn-src-all@FreeBSD.ORG Sat Jul 16 00:30:23 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E22BD106566B; Sat, 16 Jul 2011 00:30:23 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id D1EEB8FC16; Sat, 16 Jul 2011 00:30:23 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p6G0UNl9002232; Sat, 16 Jul 2011 00:30:23 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p6G0UNH5002230; Sat, 16 Jul 2011 00:30:23 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201107160030.p6G0UNH5002230@svn.freebsd.org> From: Adrian Chadd Date: Sat, 16 Jul 2011 00:30:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r224072 - head/sys/mips/malta X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 16 Jul 2011 00:30:24 -0000 Author: adrian Date: Sat Jul 16 00:30:23 2011 New Revision: 224072 URL: http://svn.freebsd.org/changeset/base/224072 Log: The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan Modified: head/sys/mips/malta/gt_pci.c Modified: head/sys/mips/malta/gt_pci.c ============================================================================== --- head/sys/mips/malta/gt_pci.c Fri Jul 15 21:37:13 2011 (r224071) +++ head/sys/mips/malta/gt_pci.c Sat Jul 16 00:30:23 2011 (r224072) @@ -326,15 +326,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_RR); /* reset, program device, 4 bytes */ @@ -348,15 +348,15 @@ gt_pci_attach(device_t dev) ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_RR); /*