From owner-freebsd-current@FreeBSD.ORG Wed Jun 16 09:46:58 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E11BC16A4CE for ; Wed, 16 Jun 2004 09:46:58 +0000 (GMT) Received: from av2-1-sn3.vrr.skanova.net (av2-1-sn3.vrr.skanova.net [81.228.9.107]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0E4A743D58 for ; Wed, 16 Jun 2004 09:46:58 +0000 (GMT) (envelope-from martin@gneto.com) Received: by av2-1-sn3.vrr.skanova.net (Postfix, from userid 502) id 7983937E7F; Wed, 16 Jun 2004 11:46:26 +0200 (CEST) Received: from smtp4-2-sn2.hy.skanova.net (smtp4-2-sn2.hy.skanova.net [81.228.8.93]) by av2-1-sn3.vrr.skanova.net (Postfix) with ESMTP id 68EB637E43; Wed, 16 Jun 2004 11:46:26 +0200 (CEST) Received: from [192.168.2.10] (h118n1fls31o985.telia.com [213.65.16.118]) by smtp4-2-sn2.hy.skanova.net (Postfix) with ESMTP id 086D937E44; Wed, 16 Jun 2004 11:46:26 +0200 (CEST) Message-ID: <40D016F2.2080904@gneto.com> Date: Wed, 16 Jun 2004 11:46:26 +0200 From: Martin Nilsson User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.7) Gecko/20040514 X-Accept-Language: sv, en-us, en MIME-Version: 1.0 To: Alexander Leidinger References: <20040616112758.46677e25@Magellan.Leidinger.net> In-Reply-To: <20040616112758.46677e25@Magellan.Leidinger.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit cc: current@freebsd.org Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2004 09:46:59 -0000 Alexander Leidinger wrote: > Now I need to know how to determine those properties on at least some > Intel CPUs (e.g. P3 & P4). The more expensive intel processors also have L3 caches of 1-4MB. Since intels processors are built with inclusive caches (data in L2 cache is also present in L3) shouldn't the value used be that of the largest cache be it L2 or L3? How much effct on performance does a wrong cache size value have? /Martin