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Date: Wed, 16 Jun 2004 11:11:02 +0100
From: Bruce M Simpson <bms@spc.org>
To: Martin Nilsson <martin@gneto.com>
Message-ID: <20040616101102.GQ32244@empiric.dek.spc.org>
References: <20040616112758.46677e25@Magellan.Leidinger.net>
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cc: Alexander Leidinger <Alexander@Leidinger.net>
cc: current@freebsd.org
Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic
	page queue color tuning)?
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On Wed, Jun 16, 2004 at 11:46:26AM +0200, Martin Nilsson wrote:
> The more expensive intel processors also have L3 caches of 1-4MB.
> Since intels processors are built with inclusive caches (data in L2 
> cache is also present in L3) shouldn't the value used be that of the 
> largest cache be it L2 or L3?
> 
> How much effct on performance does a wrong cache size value have?

Gag. I posted something on this whole subject last *year*, and still
haven't gotten round to code.

BMS