From owner-svn-src-all@freebsd.org Thu Feb 11 11:55:39 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8CC52AA5077; Thu, 11 Feb 2016 11:55:39 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 66D541E6F; Thu, 11 Feb 2016 11:55:39 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1BBtcf9050091; Thu, 11 Feb 2016 11:55:38 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1BBtcxH050087; Thu, 11 Feb 2016 11:55:38 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201602111155.u1BBtcxH050087@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Thu, 11 Feb 2016 11:55:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r295512 - in head/sys/arm64: arm64 include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Feb 2016 11:55:39 -0000 Author: zbb Date: Thu Feb 11 11:55:37 2016 New Revision: 295512 URL: https://svnweb.freebsd.org/changeset/base/295512 Log: Minor clean-ups for ARM64 GICv3 and GIC drivers GICv3: - move ICC_SGI1R_EL1 definitions to armreg.h and use proper system register's names GIC: - remove unused functions Reviewed by: andrew Obtained from: Semihalf Sponsored by: Cavium Differential Revision: https://reviews.freebsd.org/D5119 Modified: head/sys/arm64/arm64/gic.c head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_reg.h head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/gic.c ============================================================================== --- head/sys/arm64/arm64/gic.c Thu Feb 11 11:53:32 2016 (r295511) +++ head/sys/arm64/arm64/gic.c Thu Feb 11 11:55:37 2016 (r295512) @@ -303,29 +303,6 @@ gic_ipi_send(device_t dev, cpuset_t cpus gic_d_write_4(sc, GICD_SGIR(0), val | ipi); } - -static int -arm_gic_ipi_read(device_t dev, int i) -{ - - if (i != -1) { - /* - * The intr code will automagically give the frame pointer - * if the interrupt argument is 0. - */ - if ((unsigned int)i > 16) - return (0); - return (i); - } - - return (0x3ff); -} - -static void -arm_gic_ipi_clear(device_t dev, int ipi) -{ - /* no-op */ -} #endif static device_method_t arm_gic_methods[] = { Modified: head/sys/arm64/arm64/gic_v3.c ============================================================================== --- head/sys/arm64/arm64/gic_v3.c Thu Feb 11 11:53:32 2016 (r295511) +++ head/sys/arm64/arm64/gic_v3.c Thu Feb 11 11:55:37 2016 (r295512) @@ -412,14 +412,15 @@ gic_v3_ipi_send(device_t dev, cpuset_t c } } if (tlist) { - KASSERT((tlist & ~GICI_SGI_TLIST_MASK) == 0, + KASSERT((tlist & ~ICC_SGI1R_EL1_TL_MASK) == 0, ("Target list too long for GICv3 IPI")); /* Send SGI to CPUs in target list */ val = tlist; - val |= (uint64_t)CPU_AFF3(aff) << GICI_SGI_AFF3_SHIFT; - val |= (uint64_t)CPU_AFF2(aff) << GICI_SGI_AFF2_SHIFT; - val |= (uint64_t)CPU_AFF1(aff) << GICI_SGI_AFF1_SHIFT; - val |= (uint64_t)(ipi & GICI_SGI_IPI_MASK) << GICI_SGI_IPI_SHIFT; + val |= (uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT; + val |= (uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT; + val |= (uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT; + val |= (uint64_t)(ipi & ICC_SGI1R_EL1_SGIID_MASK) << + ICC_SGI1R_EL1_SGIID_SHIFT; gic_icc_write(SGI1R, val); } } Modified: head/sys/arm64/arm64/gic_v3_reg.h ============================================================================== --- head/sys/arm64/arm64/gic_v3_reg.h Thu Feb 11 11:53:32 2016 (r295511) +++ head/sys/arm64/arm64/gic_v3_reg.h Thu Feb 11 11:55:37 2016 (r295512) @@ -356,12 +356,6 @@ /* * CPU interface */ -#define GICI_SGI_TLIST_MASK (0xffffUL) -#define GICI_SGI_AFF1_SHIFT (16UL) -#define GICI_SGI_AFF2_SHIFT (32UL) -#define GICI_SGI_AFF3_SHIFT (48UL) -#define GICI_SGI_IPI_MASK (0xfUL) -#define GICI_SGI_IPI_SHIFT (24UL) /* * Registers list (ICC_xyz_EL1): Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Thu Feb 11 11:53:32 2016 (r295511) +++ head/sys/arm64/include/armreg.h Thu Feb 11 11:55:37 2016 (r295512) @@ -118,6 +118,15 @@ /* ICC_PMR_EL1 */ #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) +/* ICC_SGI1R_EL1 */ +#define ICC_SGI1R_EL1_TL_MASK 0xffffUL +#define ICC_SGI1R_EL1_AFF1_SHIFT 16 +#define ICC_SGI1R_EL1_SGIID_SHIFT 24 +#define ICC_SGI1R_EL1_AFF2_SHIFT 32 +#define ICC_SGI1R_EL1_AFF3_SHIFT 48 +#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL +#define ICC_SGI1R_EL1_IRM (0x1UL << 40) + /* ICC_SRE_EL1 */ #define ICC_SRE_EL1_SRE (1U << 0)