From owner-svn-src-all@FreeBSD.ORG Thu Mar 17 21:02:11 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from [127.0.0.1] (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by hub.freebsd.org (Postfix) with ESMTP id 7D4A4106564A; Thu, 17 Mar 2011 21:02:10 +0000 (UTC) (envelope-from jkim@FreeBSD.org) From: Jung-uk Kim To: Peter Jeremy Date: Thu, 17 Mar 2011 17:01:55 -0400 User-Agent: KMail/1.6.2 References: <201103152145.p2FLjAlt060256@svn.freebsd.org> <201103161634.08104.jkim@FreeBSD.org> <20110317195729.GA65858@server.vk2pj.dyndns.org> In-Reply-To: <20110317195729.GA65858@server.vk2pj.dyndns.org> MIME-Version: 1.0 Content-Disposition: inline Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201103171701.57546.jkim@FreeBSD.org> Cc: src-committers@freebsd.org, Roman Divacky , Bruce Evans , svn-src-head@freebsd.org, svn-src-all@freebsd.org, Maxim Dounin Subject: Re: svn commit: r219679 - head/sys/i386/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Mar 2011 21:02:11 -0000 On Thursday 17 March 2011 03:57 pm, Peter Jeremy wrote: > On 2011-Mar-16 16:34:04 -0400, Jung-uk Kim wrote: > >On Wednesday 16 March 2011 01:45 pm, Roman Divacky wrote: > >> if we drop i486 I think it makes sense to require something that > >> has at least SSE2, thus we can have the same expectations as on > >> amd64. > > I think it's stil a bit early for that - especially the SSE2 > requirement. > > >This is a proof-of-concept patch for sys/x86/isa/clock.c: > > > >http://people.freebsd.org/~jkim/clock.diff > > > >You see the complexity, just because I wanted to load 64-bit value > >atomically... :-( > > An alternative approach is to have _fetch_frequency() be > uint64_t (*_fetch_frequency)(uint64_t *); > if i386 and I486 are defined (otherwise it's just the #define > (*(p))) then initialise it to either atomic_fetch_quad_i386 or > atomic_fetch_quad_i586 as part of the CPU detection process. This > is the way bcopy() is/was handled on Pentium. > > Another approach would be to always have cmpxchg8b instructions > (followed by a suitably large NOP) always inlined in the code and > if it traps, patch the code to call a function that emulates it. I think the former makes more sense for atomic read/write because we don't need complete cmpxchg8b support but kind of movq support, actually. Thanks for the suggestion. Jung-uk Kim