From owner-svn-src-all@FreeBSD.ORG Wed Apr 2 21:06:45 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 404D2C26; Wed, 2 Apr 2014 21:06:45 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1F013C2C; Wed, 2 Apr 2014 21:06:45 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s32L6iSQ076930; Wed, 2 Apr 2014 21:06:44 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s32L6iMn076926; Wed, 2 Apr 2014 21:06:44 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404022106.s32L6iMn076926@svn.freebsd.org> From: Ian Lepore Date: Wed, 2 Apr 2014 21:06:44 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r264056 - in head/sys: arm/freescale/imx boot/fdt/dts/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Apr 2014 21:06:45 -0000 Author: ian Date: Wed Apr 2 21:06:43 2014 New Revision: 264056 URL: http://svnweb.freebsd.org/changeset/base/264056 Log: Switch imx6 to using the mpcore per-cpu event timers, but continue to use the GPT timer, which is fixed-frequency, as a timecounter. Modified: head/sys/arm/freescale/imx/files.imx6 head/sys/arm/freescale/imx/imx6_anatop.c head/sys/arm/freescale/imx/imx6_machdep.c head/sys/boot/fdt/dts/arm/imx6.dtsi Modified: head/sys/arm/freescale/imx/files.imx6 ============================================================================== --- head/sys/arm/freescale/imx/files.imx6 Wed Apr 2 20:18:17 2014 (r264055) +++ head/sys/arm/freescale/imx/files.imx6 Wed Apr 2 21:06:43 2014 (r264056) @@ -16,6 +16,7 @@ kern/kern_clocksource.c standard arm/arm/gic.c standard arm/arm/pl310.c standard arm/arm/bus_space-v6.c standard +arm/arm/mpcore_timer.c standard arm/freescale/fsl_ocotp.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx_common.c standard Modified: head/sys/arm/freescale/imx/imx6_anatop.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_anatop.c Wed Apr 2 20:18:17 2014 (r264055) +++ head/sys/arm/freescale/imx/imx6_anatop.c Wed Apr 2 21:06:43 2014 (r264056) @@ -68,6 +68,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include @@ -263,6 +264,8 @@ cpufreq_set_clock(struct imx6_anatop_sof imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR, IMX6_ANALOG_CCM_PLL_ARM_BYPASS); + + arm_tmr_change_frequency(sc->cpu_curhz / 2); } static void Modified: head/sys/arm/freescale/imx/imx6_machdep.c ============================================================================== --- head/sys/arm/freescale/imx/imx6_machdep.c Wed Apr 2 20:18:17 2014 (r264055) +++ head/sys/arm/freescale/imx/imx6_machdep.c Wed Apr 2 21:06:43 2014 (r264056) @@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include @@ -55,6 +56,8 @@ void initarm_early_init(void) { + /* Inform the MPCore timer driver that its clock is variable. */ + arm_tmr_change_frequency(ARM_TMR_FREQUENCY_VARIES); } void Modified: head/sys/boot/fdt/dts/arm/imx6.dtsi ============================================================================== --- head/sys/boot/fdt/dts/arm/imx6.dtsi Wed Apr 2 20:18:17 2014 (r264055) +++ head/sys/boot/fdt/dts/arm/imx6.dtsi Wed Apr 2 21:06:43 2014 (r264056) @@ -71,6 +71,14 @@ 0x00a00100 0x00000100>; }; + mp_tmr0@00a00200 { + compatible = "arm,mpcore-timers"; + reg = <0x00a00200 0x100 + 0x00a00600 0x100>; + interrupts = <27 29>; + interrupt-parent = <&gic>; + }; + l2-cache@00a02000 { compatible = "arm,pl310-cache", "arm,pl310"; reg = <0xa02000 0x1000>;