From owner-p4-projects@FreeBSD.ORG Fri Jan 18 06:38:40 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 5C61416A420; Fri, 18 Jan 2008 06:38:40 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 21ED316A419 for ; Fri, 18 Jan 2008 06:38:40 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id DEE9F13C46B for ; Fri, 18 Jan 2008 06:38:39 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0I6cdgF058127 for ; Fri, 18 Jan 2008 06:38:39 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0I6cdMv058124 for perforce@freebsd.org; Fri, 18 Jan 2008 06:38:39 GMT (envelope-from imp@freebsd.org) Date: Fri, 18 Jan 2008 06:38:39 GMT Message-Id: <200801180638.m0I6cdMv058124@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 133530 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Jan 2008 06:38:40 -0000 http://perforce.freebsd.org/chv.cgi?CH=133530 Change 133530 by imp@imp_paco-paco on 2008/01/18 06:38:24 Juniper cpu.c isn't quite as good as the mips2 one, in terms of info it provides and integration into the system. eliminate it. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/conf/files.mips#9 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu-mips2.c#5 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#5 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#16 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/conf/files.mips#9 (text+ko) ==== @@ -42,7 +42,6 @@ # Phase 3 # ---------------------------------------------------------------------- mips/mips/autoconf.c standard -mips/mips/cpu.c standard mips/mips/cpu-mips2.c standard mips/mips/elf_machdep.c standard mips/mips/exception.S standard ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu-mips2.c#5 (text+ko) ==== @@ -48,6 +48,9 @@ static struct mips_cpuinfo cpuinfo; +union cpuprid cpu_id; +union cpuprid fpu_id; + /* * Attempt to identify the MIPS CPU as much as possible. * ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#5 (text+ko) ==== @@ -40,31 +40,6 @@ #include #include -union cpuprid cpu_id; -union cpuprid fpu_id; - -u_int CpuPrimaryInstCacheSize; -u_int CpuPrimaryInstCacheLSize; -u_int CpuPrimaryInstSetSize; -u_int CpuPrimaryInstCacheNsets; -u_int CpuPrimaryInstCacheAsso; - -u_int CpuPrimaryDataCacheSize; -u_int CpuPrimaryDataCacheLSize; -u_int CpuPrimaryDataSetSize; -u_int CpuPrimaryDataCacheNsets; -u_int CpuPrimaryDataCacheAsso; - -u_int CpuCacheAliasMask; -u_int CpuSecondaryCacheSize; -u_int CpuTertiaryCacheSize; -u_int CpuNWayCache; -u_int CpuCacheType; -u_int CpuConfigRegister; -u_int CpuStatusRegister; -u_int CpuExternalCacheOn; -u_int CpuOnboardCacheOn; - static void cpu_identify(driver_t *driver, device_t parent); static int cpu_probe(device_t dev); static int cpu_attach(device_t dev); @@ -117,87 +92,6 @@ static int cpu_attach(device_t dev) { - printf(": "); - - switch (mips_proc_type()) { - - /* - * FREEBSD_DELVELOPERS_FIXME: - * Read the CPU-ID register and based on the - * id, print a string describing the CPU-Vendor, - * Series etc. - */ - default: - printf("Unknown CPU type (0x%x)",cpu_id.cpu.cp_imp); - break; - } - printf(" Rev. %d.%d with ", cpu_id.cpu.cp_majrev, cpu_id.cpu.cp_minrev); - - switch(fpu_id.cpu.cp_imp) { - /* - * FREEBSD_DELVELOPERS_FIXME: - * Read the FPU-ID register and based on the - * id, print a string describing the CPU-Vendor, - * Series for the FPU unit. - */ - case MIPS_SOFT: - /* No FPU Present */ - break; - - case MIPS_UNKF1: - default: - printf("Unknown FPU type (0x%x)", fpu_id.cpu.cp_imp); - break; - } - - printf(" L1 Cache: I size %dkb(%d line),", - CpuPrimaryInstCacheSize / 1024, CpuPrimaryInstCacheLSize); - printf(" D size %dkb(%d line), ", - CpuPrimaryDataCacheSize / 1024, CpuPrimaryDataCacheLSize); - - switch(CpuNWayCache) { - case 2: - printf("two way.\n"); - break; - case 4: - printf("four way.\n"); - break; - case 8: - printf("eight way.\n"); - break; - default: - printf("direct mapped.\n"); - break; - } - - if(CpuSecondaryCacheSize != 0) { - /* - * FREEBSD_DELVELOPERS_FIXME: - * Extract the L2 cache size and associativity - * for the CPU either from the registers or based - * on CPU type hard-code it here. - */ - switch(mips_proc_type()) { - default: - printf(" L2 Cache: Size %dkb, direct mapped\n", - CpuSecondaryCacheSize / 1024); - break; - } - - } - if(CpuTertiaryCacheSize != 0) { - printf(" L3 Cache: Size %dkb, direct mapped\n", - CpuTertiaryCacheSize / 1024); - } - -#ifdef DEBUG - printf("\tSetsize %d:%d\n", CpuPrimaryInstSetSize, - CpuPrimaryDataSetSize); - printf("\tAlias mask 0x%x\n", CpuCacheAliasMask); - printf("\tConfig Register %x\n",CpuConfigRegister); - printf("\tCache type %x\n", CpuCacheType); - printf("\tStatus Register %x\n",CpuStatusRegister); -#endif return 0; } ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#16 (text+ko) ==== @@ -410,11 +410,6 @@ void mips_vector_init(void) { - CpuTertiaryCacheSize = 0; - CpuExternalCacheOn = 0; /* No L3 detected */ - - CpuOnboardCacheOn = 1; - /* * Copy down exception vector code. */