From owner-freebsd-current@FreeBSD.ORG Thu Jun 17 19:32:16 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id CF3B116A4CE for ; Thu, 17 Jun 2004 19:32:16 +0000 (GMT) Received: from mail.sandvine.com (sandvine.com [199.243.201.138]) by mx1.FreeBSD.org (Postfix) with ESMTP id 1928643D1D for ; Thu, 17 Jun 2004 19:32:16 +0000 (GMT) (envelope-from don@sandvine.com) Received: by mail.sandvine.com with Internet Mail Service (5.5.2657.72) id ; Thu, 17 Jun 2004 15:32:04 -0400 Message-ID: From: Don Bowman To: "'current@freebsd.org'" Date: Thu, 17 Jun 2004 15:32:03 -0400 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2657.72) Content-Type: text/plain; charset="iso-8859-1" Subject: STI, HLT in acpi_cpu_idle_c1 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jun 2004 19:32:16 -0000 in the intel instruction manual, the effect of STI is that interrupts are enabled *after* the next instruction. ie: sti ret ... the return is still run with interrupts disabled (if they were prior to the STI). In acpi_cpu_idle_c1, it does: sti hlt shouldn't there be a NOP in there so that interrupts are guaranteed on? We have traced down a lockup of the system with a TAP emulator, and found that three processors are in acpi_cpu_idle with bit 9 of EFLAGS clear, indicating interrupts are disabled. The fourth processor is spinning with nothing to do (since hardclock etc don't come to it). Suggestions? Am i off base on the sti/hlt? Is there another problem that i might be running into? --don