From owner-svn-src-all@FreeBSD.ORG Fri Nov 15 07:26:51 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C6959313; Fri, 15 Nov 2013 07:26:51 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id B567E2378; Fri, 15 Nov 2013 07:26:51 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rAF7QpCq097895; Fri, 15 Nov 2013 07:26:51 GMT (envelope-from kib@svn.freebsd.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id rAF7Qojh097890; Fri, 15 Nov 2013 07:26:50 GMT (envelope-from kib@svn.freebsd.org) Message-Id: <201311150726.rAF7Qojh097890@svn.freebsd.org> From: Konstantin Belousov Date: Fri, 15 Nov 2013 07:26:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r258161 - in stable/9/sys: amd64/amd64 amd64/include i386/i386 i386/include X-SVN-Group: stable-9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Nov 2013 07:26:52 -0000 Author: kib Date: Fri Nov 15 07:26:50 2013 New Revision: 258161 URL: http://svnweb.freebsd.org/changeset/base/258161 Log: MFC r257856: Add bits for the AMD features from CPUID function 0x80000001 ECX, described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf. Modified: stable/9/sys/amd64/amd64/identcpu.c stable/9/sys/amd64/include/specialreg.h stable/9/sys/i386/i386/identcpu.c stable/9/sys/i386/include/specialreg.h Directory Properties: stable/9/sys/ (props changed) Modified: stable/9/sys/amd64/amd64/identcpu.c ============================================================================== --- stable/9/sys/amd64/amd64/identcpu.c Fri Nov 15 07:14:01 2013 (r258160) +++ stable/9/sys/amd64/amd64/identcpu.c Fri Nov 15 07:26:50 2013 (r258161) @@ -366,18 +366,18 @@ printcpuinfo(void) "\017" "\020LWP" /* Lightweight Profiling */ "\021FMA4" /* 4-operand FMA instructions */ - "\022" + "\022TCE" /* Translation Cache Extension */ "\023" "\024NodeId" /* NodeId MSR support */ "\025" "\026TBM" /* Trailing Bit Manipulation */ "\027Topology" /* Topology Extensions */ - "\030" - "\031" + "\030PCXC" /* Core perf count */ + "\031PNXC" /* NB perf count */ "\032" - "\033" - "\034" - "\035" + "\033DBE" /* Data Breakpoint extension */ + "\034PTSC" /* Performance TSC */ + "\035PL2I" /* L2I perf count */ "\036" "\037" "\040" Modified: stable/9/sys/amd64/include/specialreg.h ============================================================================== --- stable/9/sys/amd64/include/specialreg.h Fri Nov 15 07:14:01 2013 (r258160) +++ stable/9/sys/amd64/include/specialreg.h Fri Nov 15 07:26:50 2013 (r258161) @@ -201,9 +201,15 @@ #define AMDID2_WDT 0x00002000 #define AMDID2_LWP 0x00008000 #define AMDID2_FMA4 0x00010000 +#define AMDID2_TCE 0x00020000 #define AMDID2_NODE_ID 0x00080000 #define AMDID2_TBM 0x00200000 #define AMDID2_TOPOLOGY 0x00400000 +#define AMDID2_PCXC 0x00800000 +#define AMDID2_PNXC 0x01000000 +#define AMDID2_DBE 0x04000000 +#define AMDID2_PTSC 0x08000000 +#define AMDID2_PTSCEL2I 0x10000000 /* * CPUID instruction 1 eax info Modified: stable/9/sys/i386/i386/identcpu.c ============================================================================== --- stable/9/sys/i386/i386/identcpu.c Fri Nov 15 07:14:01 2013 (r258160) +++ stable/9/sys/i386/i386/identcpu.c Fri Nov 15 07:26:50 2013 (r258161) @@ -842,18 +842,18 @@ printcpuinfo(void) "\017" "\020LWP" /* Lightweight Profiling */ "\021FMA4" /* 4-operand FMA instructions */ - "\022" + "\022TCE" /* Translation Cache Extension */ "\023" "\024NodeId" /* NodeId MSR support */ "\025" "\026TBM" /* Trailing Bit Manipulation */ "\027Topology" /* Topology Extensions */ - "\030" - "\031" + "\030PCXC" /* Core perf count */ + "\031PNXC" /* NB perf count */ "\032" - "\033" - "\034" - "\035" + "\033DBE" /* Data Breakpoint extension */ + "\034PTSC" /* Performance TSC */ + "\035PL2I" /* L2I perf count */ "\036" "\037" "\040" Modified: stable/9/sys/i386/include/specialreg.h ============================================================================== --- stable/9/sys/i386/include/specialreg.h Fri Nov 15 07:14:01 2013 (r258160) +++ stable/9/sys/i386/include/specialreg.h Fri Nov 15 07:26:50 2013 (r258161) @@ -180,9 +180,15 @@ #define AMDID2_WDT 0x00002000 #define AMDID2_LWP 0x00008000 #define AMDID2_FMA4 0x00010000 +#define AMDID2_TCE 0x00020000 #define AMDID2_NODE_ID 0x00080000 #define AMDID2_TBM 0x00200000 #define AMDID2_TOPOLOGY 0x00400000 +#define AMDID2_PCXC 0x00800000 +#define AMDID2_PNXC 0x01000000 +#define AMDID2_DBE 0x04000000 +#define AMDID2_PTSC 0x08000000 +#define AMDID2_PTSCEL2I 0x10000000 /* * CPUID instruction 1 eax info