From owner-freebsd-current@FreeBSD.ORG Thu Jun 17 20:37:05 2004 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 1BD2016A4CE for ; Thu, 17 Jun 2004 20:37:05 +0000 (GMT) Received: from mail.sandvine.com (sandvine.com [199.243.201.138]) by mx1.FreeBSD.org (Postfix) with ESMTP id 7FADD43D31 for ; Thu, 17 Jun 2004 20:37:04 +0000 (GMT) (envelope-from don@sandvine.com) Received: by mail.sandvine.com with Internet Mail Service (5.5.2657.72) id ; Thu, 17 Jun 2004 16:36:53 -0400 Message-ID: From: Don Bowman To: 'Matthew Dillon' , Don Bowman Date: Thu, 17 Jun 2004 16:36:51 -0400 MIME-Version: 1.0 X-Mailer: Internet Mail Service (5.5.2657.72) Content-Type: text/plain; charset="iso-8859-1" cc: Julian Elischer cc: "'current@freebsd.org'" Subject: RE: STI, HLT in acpi_cpu_idle_c1 X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jun 2004 20:37:05 -0000 From: Matthew Dillon [mailto:dillon@apollo.backplane.com] ... OK, i understand. > > So, if the emulator is not coming out of the HLT it's a > bug in the > emulator. The STI; HLT sequence is correct. The emulator is doing the right thing. It breaks the processors out, and shows all the registers etc. Its transparent, done via jtag (American Arium). In the lockup case i have, 3 processors are executing HLT, and EFLAGS bit 9 is clear. Thus I was wondering, it doesn't seem obvious as to where in the pipeline the STI will take affect. Is it at the end of the HLT instruction? Is this 'end' when an interrupt occurs? The manual just says "after the next instruction". Does that mean the instruction following needs to start? Does the halt instruction 'end' when the processor goes to sleep, or when the processor wakes up? What should I expect to see in bit 9 of eflags when i'm executing HLT? I can't otherwise find how my system is behaving. The processors will service an NMI in this mode, as i would expect, but will not service any normal interrupts (serial, lan, hardclock). The sole 'awake' processor doesn't have any physical interrupts routed to it, and the ones that do have the physical interrupts have interrupts disabled. I added a hack into ddb so that I could NMI in in this case without hanging, and it finds that the IPI it sends to the other processors doesn't get answered: they don't stop. So I have reverted to the hardware ICE in order to find what is going on. --don