From owner-freebsd-usb@FreeBSD.ORG  Wed Jan 30 15:54:10 2008
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Date: Wed, 30 Jan 2008 16:20:53 +0100
From: Rafal Jaworowski <raj@semihalf.com>
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Subject: USB transfer coherency problems with write-allocate caches
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Hi,

While working on an ARM SoC port, we have ecountered problems with USB
transfer incoherencies on the border of busdma and d-cache enabled for
write-allocate.

This is observed with umass(4)/EHCI and mainfests with the following error:

umass0: Invalid CSW: tag 1 should be 2
(probe0:umass-sim0:0:0:0): Request completed with CAM_REQ_CMP_ERR
(probe0:umass-sim0:0:0:0): Retrying Command
umass0: Invalid CSW: tag 1 should be 3
(probe0:umass-sim0:0:0:0): Request completed with CAM_REQ_CMP_ERR
(probe0:umass-sim0:0:0:0): Retrying Command
umass0: Invalid CSW: tag 1 should be 4
(probe0:umass-sim0:0:0:0): Request completed with CAM_REQ_CMP_ERR
(probe0:umass-sim0:0:0:0): Retrying Command
umass0: Invalid CSW: tag 1 should be 5
(probe0:umass-sim0:0:0:0): Request completed with CAM_REQ_CMP_ERR
(probe0:umass-sim0:0:0:0): Retrying Command
umass0: Invalid CSW: tag 1 should be 6
(probe0:umass-sim0:0:0:0): Request completed with CAM_REQ_CMP_ERR
(probe0:umass-sim0:0:0:0): error 5
(probe0:umass-sim0:0:0:0): Retries Exausted

Because of the way write-allocate works, we can end up having an old and
un-flushed CSW in the cache (from a previous transaction) overwrite the newly
arrived CSW, and hence the tags inconsistencies.

Doing a BUS_DMASYNC_PREREAD in usbd_start_transfer() fixes the problems, see
this patch:

http://people.freebsd.org/~raj/patches/misc/usbdi-bus_dma-fix.diff

I'd like to hear comments from people knowing other architectures if they have
any comments/objections.

Rafal

PS. Please keep me on CC as I'm not subscribed to the list.