From owner-svn-src-all@FreeBSD.ORG Sat Dec 1 18:16:14 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id C27CA4D1; Sat, 1 Dec 2012 18:16:14 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 8EFC68FC14; Sat, 1 Dec 2012 18:16:14 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qB1IGE2l064319; Sat, 1 Dec 2012 18:16:14 GMT (envelope-from avg@svn.freebsd.org) Received: (from avg@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qB1IGE2Y064317; Sat, 1 Dec 2012 18:16:14 GMT (envelope-from avg@svn.freebsd.org) Message-Id: <201212011816.qB1IGE2Y064317@svn.freebsd.org> From: Andriy Gapon Date: Sat, 1 Dec 2012 18:16:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243764 - head/sys/x86/x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2012 18:16:14 -0000 Author: avg Date: Sat Dec 1 18:16:14 2012 New Revision: 243764 URL: http://svnweb.freebsd.org/changeset/base/243764 Log: ioapic_program_intpin: program high bits before low bits Programming the low bits has a side-effect if unmasking the pin if it is not disabled. So if an interrupt was pending then it would be delivered with the correct new vector but to the incorrect old LAPIC. This fix could be made clearer by preserving the mask bit while programming the low bits and then explicitly resetting the mask bit after all the programming is done. Probability to trip over the fixed bug could be increased by bootverbose because printing of the interrupt information in ioapic_assign_cpu lengthened the time window during which an interrupt could arrive while a pin is masked. Reported by: Andreas Longwitz Tested by: Andreas Longwitz MFC after: 12 days Modified: head/sys/x86/x86/io_apic.c Modified: head/sys/x86/x86/io_apic.c ============================================================================== --- head/sys/x86/x86/io_apic.c Sat Dec 1 18:13:53 2012 (r243763) +++ head/sys/x86/x86/io_apic.c Sat Dec 1 18:16:14 2012 (r243764) @@ -311,12 +311,12 @@ ioapic_program_intpin(struct ioapic_ints } /* Write the values to the APIC. */ - intpin->io_lowreg = low; - ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); value &= ~IOART_DEST; value |= high; ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); + intpin->io_lowreg = low; + ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); } static int