From owner-p4-projects@FreeBSD.ORG Tue Nov 28 08:43:16 2006 Return-Path: X-Original-To: p4-projects@freebsd.org Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id ECDEA16A494; Tue, 28 Nov 2006 08:43:15 +0000 (UTC) X-Original-To: perforce@freebsd.org Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 7C16D16A54B for ; Tue, 28 Nov 2006 08:43:15 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [69.147.83.41]) by mx1.FreeBSD.org (Postfix) with ESMTP id F001943CBA for ; Tue, 28 Nov 2006 08:43:13 +0000 (GMT) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.13.6/8.13.6) with ESMTP id kAS8hEdA013704 for ; Tue, 28 Nov 2006 08:43:14 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.13.6/8.13.4/Submit) id kAS8hEeV013701 for perforce@freebsd.org; Tue, 28 Nov 2006 08:43:14 GMT (envelope-from imp@freebsd.org) Date: Tue, 28 Nov 2006 08:43:14 GMT Message-Id: <200611280843.kAS8hEeV013701@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 110618 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2006 08:43:16 -0000 http://perforce.freebsd.org/chv.cgi?CH=110618 Change 110618 by imp@imp_lighthouse on 2006/11/28 08:42:52 Careful reading of the datasheet shows that we don't have to do a complete read when we do a right. Rather, we just need to start *A* read, even if it is for 0 bytes. The lockout mechanism is will release access to the chip. In fact, we could likely get away with not bothering to do this at all, since the very next write will stall. Better safe than sorry until I can get more experience. In addition, careful study of the larger parts shows that the 16 bit parts > 64KB could have additional bits set in the slave address. Also, it is most significant byte first, not least, so fix that while I'm here. Affected files ... .. //depot/projects/arm/src/sys/dev/iicbus/icee.c#4 edit Differences ... ==== //depot/projects/arm/src/sys/dev/iicbus/icee.c#4 (text+ko) ==== @@ -44,7 +44,7 @@ #define IIC_M_WR 0 /* write operation */ #define MAX_RD_SZ 256 /* Largest read size we support */ -#define MAX_WR_SZ 16 /* Largest write size we support */ +#define MAX_WR_SZ 256 /* Largest write size we support */ struct icee_softc { device_t sc_dev; /* Myself */ @@ -182,11 +182,12 @@ break; case 16: for (i = 0; i < 2; i++) - msgs[i].slave = sc->addr; + msgs[i].slave = sc->addr | + uio->uio_offset >> 16; msgs[0].len = 2; msgs[1].len = len; - addr[0] = uio->uio_offset & 0xff; - addr[1] = (uio->uio_offset >> 8) & 0xff; + addr[0] = (uio->uio_offset >> 8) & 0xff; + addr[1] = uio->uio_offset & 0xff; break; } error = iicbus_transfer(sc->sc_dev, msgs, 2); @@ -214,7 +215,6 @@ uint8_t data[MAX_WR_SZ + 2]; struct iic_msg msgs[3] = { { 0, IIC_M_WR, 0, data }, - { 0, IIC_M_WR, 0, data }, { 0, IIC_M_RD, 0, data }, }; @@ -235,26 +235,23 @@ break; switch (sc->type) { case 8: - for (i = 0; i < 3; i++) + for (i = 0; i < 2; i++) msgs[i].slave = uio->uio_offset >> 8 | sc->addr; msgs[0].len = 1 + len; - msgs[1].len = 1; - msgs[2].len = 1; - msgs[2].buf = data + 1; + msgs[1].len = 0; data[0] = uio->uio_offset & 0xff; break; case 16: - for (i = 0; i < 3; i++) - msgs[i].slave = sc->addr; + for (i = 0; i < 2; i++) + msgs[i].slave = sc->addr | + uio->uio_offset >> 16; msgs[0].len = 2 + len; - msgs[1].len = 2; - msgs[2].len = 1; - msgs[2].buf = data + 2; - data[0] = uio->uio_offset & 0xff; - data[1] = (uio->uio_offset >> 8) & 0xff; + msgs[1].len = 0; + data[0] = (uio->uio_offset >> 8) & 0xff; + data[1] = uio->uio_offset & 0xff; break; } - error = iicbus_transfer(sc->sc_dev, msgs, 3); + error = iicbus_transfer(sc->sc_dev, msgs, 2); if (error) break; }