From owner-svn-src-stable@FreeBSD.ORG Fri Jan 31 03:38:23 2014 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id AD380458; Fri, 31 Jan 2014 03:38:23 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 9727E1437; Fri, 31 Jan 2014 03:38:23 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id s0V3cNOD087189; Fri, 31 Jan 2014 03:38:23 GMT (envelope-from pfg@svn.freebsd.org) Received: (from pfg@localhost) by svn.freebsd.org (8.14.7/8.14.7/Submit) id s0V3cMR8087184; Fri, 31 Jan 2014 03:38:22 GMT (envelope-from pfg@svn.freebsd.org) Message-Id: <201401310338.s0V3cMR8087184@svn.freebsd.org> From: "Pedro F. Giffuni" Date: Fri, 31 Jan 2014 03:38:22 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r261307 - in stable/10/contrib/binutils: gas/config opcodes X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Jan 2014 03:38:23 -0000 Author: pfg Date: Fri Jan 31 03:38:22 2014 New Revision: 261307 URL: http://svnweb.freebsd.org/changeset/base/261307 Log: MFC r261175: binutils: add support for Intel SMAP-related instructions Add support for stac/clac instructions to manipulate the flag that controls the behaviour of Intel's Supervisor Mode Access Prevention (SMAP) feature. Tested by: dim Obtained from: OpenBSD Modified: stable/10/contrib/binutils/gas/config/tc-i386.c stable/10/contrib/binutils/opcodes/i386-dis.c stable/10/contrib/binutils/opcodes/i386-opc.h stable/10/contrib/binutils/opcodes/i386-tbl.h Directory Properties: stable/10/ (props changed) Modified: stable/10/contrib/binutils/gas/config/tc-i386.c ============================================================================== --- stable/10/contrib/binutils/gas/config/tc-i386.c Fri Jan 31 03:30:09 2014 (r261306) +++ stable/10/contrib/binutils/gas/config/tc-i386.c Fri Jan 31 03:38:22 2014 (r261307) @@ -1827,7 +1827,7 @@ md_assemble (line) { expressionS *exp; - if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0) + if ((i.tm.cpu_flags & (CpuSSE3|CpuSMAP)) && i.operands > 0) { /* Streaming SIMD extensions 3 Instructions have the fixed operands with an opcode suffix which is coded in the same Modified: stable/10/contrib/binutils/opcodes/i386-dis.c ============================================================================== --- stable/10/contrib/binutils/opcodes/i386-dis.c Fri Jan 31 03:30:09 2014 (r261306) +++ stable/10/contrib/binutils/opcodes/i386-dis.c Fri Jan 31 03:38:22 2014 (r261307) @@ -6257,6 +6257,16 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSE codep++; } + else if (modrm.mod == 3 && modrm.reg == 1 && modrm.rm <= 3) + { + size_t olen = strlen (obuf); + char *p = obuf + olen - 4; + if (*codep == 0xca) + strcpy (p, "clac"); + else if (*codep == 0xcb) + strcpy (p, "stac"); + codep++; + } else OP_M (0, sizeflag); } Modified: stable/10/contrib/binutils/opcodes/i386-opc.h ============================================================================== --- stable/10/contrib/binutils/opcodes/i386-opc.h Fri Jan 31 03:30:09 2014 (r261306) +++ stable/10/contrib/binutils/opcodes/i386-opc.h Fri Jan 31 03:38:22 2014 (r261307) @@ -80,6 +80,7 @@ typedef struct template #define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */ #define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */ +#define CpuSMAP 0x40000000 /* Intel Supervisor Mode Access Prevention */ /* SSE4.1/4.2 Instructions required */ #define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) @@ -88,7 +89,7 @@ typedef struct template #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ - |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd) + |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of Modified: stable/10/contrib/binutils/opcodes/i386-tbl.h ============================================================================== --- stable/10/contrib/binutils/opcodes/i386-tbl.h Fri Jan 31 03:30:09 2014 (r261306) +++ stable/10/contrib/binutils/opcodes/i386-tbl.h Fri Jan 31 03:38:22 2014 (r261307) @@ -4379,6 +4379,12 @@ const template i386_optab[] = {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|NoSuf, { Reg16|Reg32|Reg64 } }, + + /* Intel Supervisor Mode Access Prevention extensions */ + {"clac", 0, 0x0f01, 0xca, CpuSMAP, + NoSuf|ImmExt, { 0, 0, 0 } }, + {"stac", 0, 0x0f01, 0xcb, CpuSMAP, + NoSuf|ImmExt, { 0, 0, 0 } }, { NULL, 0, 0, 0, 0, 0, { 0 } } };