From owner-svn-src-all@FreeBSD.ORG Sat May 10 08:10:02 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 3DE7FF65; Sat, 10 May 2014 08:10:02 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2B440176; Sat, 10 May 2014 08:10:02 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s4A8A2vX082925; Sat, 10 May 2014 08:10:02 GMT (envelope-from rpaulo@svn.freebsd.org) Received: (from rpaulo@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s4A8A29Q082924; Sat, 10 May 2014 08:10:02 GMT (envelope-from rpaulo@svn.freebsd.org) Message-Id: <201405100810.s4A8A29Q082924@svn.freebsd.org> From: Rui Paulo Date: Sat, 10 May 2014 08:10:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r265810 - stable/10/sys/arm/ti X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 May 2014 08:10:02 -0000 Author: rpaulo Date: Sat May 10 08:10:01 2014 New Revision: 265810 URL: http://svnweb.freebsd.org/changeset/base/265810 Log: MFC r259126: Activate the device before attempt to access any of its registers. Without this change we may end up with a panic (Fatal kernel mode data abort: 'External Non-Linefetch Abort (S)') as described in http://e2e.ti.com/support/arm/sitara_arm/f/791/t/276862.aspx. It is now possible to bring up I2C1 and I2C2 on BBB. Modified: stable/10/sys/arm/ti/ti_i2c.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/ti/ti_i2c.c ============================================================================== --- stable/10/sys/arm/ti/ti_i2c.c Sat May 10 08:07:41 2014 (r265809) +++ stable/10/sys/arm/ti/ti_i2c.c Sat May 10 08:10:01 2014 (r265810) @@ -1076,20 +1076,20 @@ ti_i2c_attach(device_t dev) goto out; } - /* XXXOMAP3: FIXME get proper revision here */ - /* First read the version number of the I2C module */ - sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; - - device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4, - sc->sc_rev & 0xf); - - /* Activate the H/W */ + /* First we _must_ activate the H/W */ err = ti_i2c_activate(dev); if (err) { device_printf(dev, "ti_i2c_activate failed\n"); goto out; } + /* XXXOMAP3: FIXME get proper revision here */ + /* Read the version number of the I2C module */ + sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; + + device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4, + sc->sc_rev & 0xf); + /* activate the interrupt */ err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_i2c_intr, sc, &sc->sc_irq_h);