From owner-svn-src-all@FreeBSD.ORG Sat May 10 13:16:05 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 9D8B9CCE; Sat, 10 May 2014 13:16:05 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 71125C7D; Sat, 10 May 2014 13:16:05 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s4ADG5r5017697; Sat, 10 May 2014 13:16:05 GMT (envelope-from loos@svn.freebsd.org) Received: (from loos@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s4ADG5Ib017696; Sat, 10 May 2014 13:16:05 GMT (envelope-from loos@svn.freebsd.org) Message-Id: <201405101316.s4ADG5Ib017696@svn.freebsd.org> From: Luiz Otavio O Souza Date: Sat, 10 May 2014 13:16:05 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265816 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 May 2014 13:16:05 -0000 Author: loos Date: Sat May 10 13:16:04 2014 New Revision: 265816 URL: http://svnweb.freebsd.org/changeset/base/265816 Log: Do not configure all pins as outputs as this can lead to short circuits when the GPIO pin is connected to a push button (or other devices). Instead keep the boot loader settings. Calling ar71xx_gpio_pin_configure() with DEFAULT_CAPS was probably a mistake and was causing all the pins to be set as outputs. Modified: head/sys/mips/atheros/ar71xx_gpio.c Modified: head/sys/mips/atheros/ar71xx_gpio.c ============================================================================== --- head/sys/mips/atheros/ar71xx_gpio.c Sat May 10 13:10:42 2014 (r265815) +++ head/sys/mips/atheros/ar71xx_gpio.c Sat May 10 13:16:04 2014 (r265816) @@ -352,6 +352,7 @@ ar71xx_gpio_attach(device_t dev) int error = 0; int i, j, maxpin; int mask, pinon; + uint32_t oe; KASSERT((device_get_unit(dev) == 0), ("ar71xx_gpio: Only one gpio module supported")); @@ -398,8 +399,7 @@ ar71xx_gpio_attach(device_t dev) ar71xx_gpio_function_disable(sc, mask); } - /* Configure all pins as input */ - /* disable interrupts for all pins */ + /* Disable interrupts for all pins. */ GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0); /* Initialise all pins specified in the mask, up to the pin count */ @@ -416,6 +416,8 @@ ar71xx_gpio_attach(device_t dev) continue; sc->gpio_npins++; } + /* Iniatilize the GPIO pins, keep the loader settings. */ + oe = GPIO_READ(sc, AR71XX_GPIO_OE); sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins, M_DEVBUF, M_WAITOK | M_ZERO); for (i = 0, j = 0; j <= maxpin; j++) { @@ -425,8 +427,10 @@ ar71xx_gpio_attach(device_t dev) "pin %d", j); sc->gpio_pins[i].gp_pin = j; sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; - sc->gpio_pins[i].gp_flags = 0; - ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS); + if (oe & (1 << j)) + sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT; + else + sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT; i++; } /* Turn on the hinted pins. */