From owner-svn-src-all@FreeBSD.ORG Sat May 10 20:03:06 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id A854C600; Sat, 10 May 2014 20:03:06 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 93E17395; Sat, 10 May 2014 20:03:06 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s4AK36nV013155; Sat, 10 May 2014 20:03:06 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s4AK34sK013136; Sat, 10 May 2014 20:03:04 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201405102003.s4AK34sK013136@svn.freebsd.org> From: Ian Lepore Date: Sat, 10 May 2014 20:03:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265852 - in head/sys/arm: at91 cavium/cns11xx mv mv/orion s3c2xx0 xscale/i80321 xscale/i8134x xscale/ixp425 xscale/pxa X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 10 May 2014 20:03:06 -0000 Author: ian Date: Sat May 10 20:03:03 2014 New Revision: 265852 URL: http://svnweb.freebsd.org/changeset/base/265852 Log: When mapping device memory, use PTE_DEVICE rather than PTE_NOCACHE. On armv4 these are defined as synonyms right now, but it's a bit ambiguous what NOCACHE means (is buffering/write-combining also enabled or not?); this is a first step towards replacing PTE_NOCACHE with a less ambiguous name. Modified: head/sys/arm/at91/at91_machdep.c head/sys/arm/cavium/cns11xx/econa_machdep.c head/sys/arm/mv/mv_localbus.c head/sys/arm/mv/mv_machdep.c head/sys/arm/mv/mv_pci.c head/sys/arm/mv/orion/db88f5xxx.c head/sys/arm/s3c2xx0/s3c24x0_machdep.c head/sys/arm/xscale/i80321/ep80219_machdep.c head/sys/arm/xscale/i80321/iq31244_machdep.c head/sys/arm/xscale/i8134x/crb_machdep.c head/sys/arm/xscale/ixp425/avila_machdep.c head/sys/arm/xscale/pxa/pxa_machdep.c Modified: head/sys/arm/at91/at91_machdep.c ============================================================================== --- head/sys/arm/at91/at91_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/at91/at91_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -126,7 +126,7 @@ const struct arm_devmap_entry at91_devma 0xfff00000, 0x00100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, /* There's a notion that we should do the rest of these lazily. */ /* @@ -150,7 +150,7 @@ const struct arm_devmap_entry at91_devma AT91RM92_OHCI_BASE, 0x00100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* CompactFlash controller. Portion of EBI CS4 1MB */ @@ -158,7 +158,7 @@ const struct arm_devmap_entry at91_devma AT91RM92_CF_BASE, 0x00100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, /* * The next two should be good for the 9260, 9261 and 9G20 since @@ -170,7 +170,7 @@ const struct arm_devmap_entry at91_devma AT91SAM9G20_OHCI_BASE, 0x00100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* EBI CS3 256MB */ @@ -178,7 +178,7 @@ const struct arm_devmap_entry at91_devma AT91SAM9G20_NAND_BASE, AT91SAM9G20_NAND_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, /* * The next should be good for the 9G45. @@ -189,7 +189,7 @@ const struct arm_devmap_entry at91_devma AT91SAM9G45_OHCI_BASE, 0x00100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, 0, 0, 0, 0, } }; Modified: head/sys/arm/cavium/cns11xx/econa_machdep.c ============================================================================== --- head/sys/arm/cavium/cns11xx/econa_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/cavium/cns11xx/econa_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -112,7 +112,7 @@ static const struct arm_devmap_entry eco ECONA_SDRAM_BASE, /*physical*/ ECONA_SDRAM_SIZE, /*size*/ VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, /* * Map the on-board devices VA == PA so that we can access them @@ -127,7 +127,7 @@ static const struct arm_devmap_entry eco ECONA_IO_BASE, /*physical*/ ECONA_IO_SIZE, /*size*/ VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* @@ -137,7 +137,7 @@ static const struct arm_devmap_entry eco ECONA_OHCI_PBASE, /*physical*/ ECONA_USB_SIZE, /*size*/ VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* @@ -147,7 +147,7 @@ static const struct arm_devmap_entry eco ECONA_CFI_PBASE, /*physical*/ ECONA_CFI_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, Modified: head/sys/arm/mv/mv_localbus.c ============================================================================== --- head/sys/arm/mv/mv_localbus.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/mv/mv_localbus.c Sat May 10 20:03:03 2014 (r265852) @@ -477,7 +477,7 @@ fdt_localbus_devmap(phandle_t dt_node, s fdt_devmap[j].pd_pa = offset; fdt_devmap[j].pd_size = size; fdt_devmap[j].pd_prot = VM_PROT_READ | VM_PROT_WRITE; - fdt_devmap[j].pd_cache = PTE_NOCACHE; + fdt_devmap[j].pd_cache = PTE_DEVICE; /* Copy data to structure used by localbus driver */ localbus_banks[bank].va = fdt_devmap[j].pd_va; Modified: head/sys/arm/mv/mv_machdep.c ============================================================================== --- head/sys/arm/mv/mv_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/mv/mv_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -284,7 +284,7 @@ moveon: map->pd_pa = base; map->pd_size = size; map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; - map->pd_cache = PTE_NOCACHE; + map->pd_cache = PTE_DEVICE; return (0); out: @@ -350,7 +350,7 @@ initarm_devmap_init(void) fdt_devmap[i].pd_pa = fdt_immr_pa; fdt_devmap[i].pd_size = fdt_immr_size; fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; - fdt_devmap[i].pd_cache = PTE_NOCACHE; + fdt_devmap[i].pd_cache = PTE_DEVICE; i++; /* Modified: head/sys/arm/mv/mv_pci.c ============================================================================== --- head/sys/arm/mv/mv_pci.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/mv/mv_pci.c Sat May 10 20:03:03 2014 (r265852) @@ -235,14 +235,14 @@ mv_pci_devmap(phandle_t node, struct arm devmap->pd_pa = io_space.base_parent; devmap->pd_size = io_space.len; devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; - devmap->pd_cache = PTE_NOCACHE; + devmap->pd_cache = PTE_DEVICE; devmap++; devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); devmap->pd_pa = mem_space.base_parent; devmap->pd_size = mem_space.len; devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; - devmap->pd_cache = PTE_NOCACHE; + devmap->pd_cache = PTE_DEVICE; return (0); } Modified: head/sys/arm/mv/orion/db88f5xxx.c ============================================================================== --- head/sys/arm/mv/orion/db88f5xxx.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/mv/orion/db88f5xxx.c Sat May 10 20:03:03 2014 (r265852) @@ -84,42 +84,42 @@ const struct pmap_devmap pmap_devmap[] = MV_PHYS_BASE, MV_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* PCIE I/O */ MV_PCIE_IO_BASE, MV_PCIE_IO_PHYS_BASE, MV_PCIE_IO_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* PCIE Memory */ MV_PCIE_MEM_BASE, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* PCI I/O */ MV_PCI_IO_BASE, MV_PCI_IO_PHYS_BASE, MV_PCI_IO_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* PCI Memory */ MV_PCI_MEM_BASE, MV_PCI_MEM_PHYS_BASE, MV_PCI_MEM_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* 7-seg LED */ MV_DEV_CS0_BASE, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, VM_PROT_READ | VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, 0, 0, 0, 0, } }; Modified: head/sys/arm/s3c2xx0/s3c24x0_machdep.c ============================================================================== --- head/sys/arm/s3c2xx0/s3c24x0_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/s3c2xx0/s3c24x0_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -130,42 +130,42 @@ static const struct arm_devmap_entry s3c _A(S3C24X0_CLKMAN_PA_BASE), _S(S3C24X0_CLKMAN_SIZE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { _A(S3C24X0_GPIO_BASE), _A(S3C24X0_GPIO_PA_BASE), _S(S3C2410_GPIO_SIZE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { _A(S3C24X0_INTCTL_BASE), _A(S3C24X0_INTCTL_PA_BASE), _S(S3C24X0_INTCTL_SIZE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { _A(S3C24X0_TIMER_BASE), _A(S3C24X0_TIMER_PA_BASE), _S(S3C24X0_TIMER_SIZE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { _A(S3C24X0_UART0_BASE), _A(S3C24X0_UART0_PA_BASE), _S(S3C24X0_UART_PA_BASE(3) - S3C24X0_UART0_PA_BASE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { _A(S3C24X0_WDT_BASE), _A(S3C24X0_WDT_PA_BASE), _S(S3C24X0_WDT_SIZE), VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, Modified: head/sys/arm/xscale/i80321/ep80219_machdep.c ============================================================================== --- head/sys/arm/xscale/i80321/ep80219_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/xscale/i80321/ep80219_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -130,21 +130,21 @@ static const struct arm_devmap_entry ep8 IQ80321_OBIO_BASE, IQ80321_OBIO_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { IQ80321_IOW_VBASE, VERDE_OUT_XLATE_IO_WIN0_BASE, VERDE_OUT_XLATE_IO_WIN_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { IQ80321_80321_VBASE, VERDE_PMMR_BASE, VERDE_PMMR_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, Modified: head/sys/arm/xscale/i80321/iq31244_machdep.c ============================================================================== --- head/sys/arm/xscale/i80321/iq31244_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/xscale/i80321/iq31244_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -128,14 +128,14 @@ static const struct arm_devmap_entry iq8 IQ80321_OBIO_BASE, IQ80321_OBIO_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { IQ80321_IOW_VBASE, VERDE_OUT_XLATE_IO_WIN0_BASE, VERDE_OUT_XLATE_IO_WIN_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { @@ -143,7 +143,7 @@ static const struct arm_devmap_entry iq8 VERDE_PMMR_BASE, VERDE_PMMR_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, Modified: head/sys/arm/xscale/i8134x/crb_machdep.c ============================================================================== --- head/sys/arm/xscale/i8134x/crb_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/xscale/i8134x/crb_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -124,7 +124,7 @@ static const struct arm_devmap_entry iq8 IOP34X_HWADDR, IOP34X_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { /* @@ -135,14 +135,14 @@ static const struct arm_devmap_entry iq8 IOP34X_PCIX_OIOBAR &~ (0x100000 - 1), 0x100000, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { IOP34X_PCE1_VADDR, IOP34X_PCE1, IOP34X_PCE1_SIZE, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, Modified: head/sys/arm/xscale/ixp425/avila_machdep.c ============================================================================== --- head/sys/arm/xscale/ixp425/avila_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/xscale/ixp425/avila_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -118,31 +118,31 @@ struct pv_addr minidataclean; static const struct arm_devmap_entry ixp425_devmap[] = { /* Physical/Virtual address for I/O space */ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* Expansion Bus */ { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* CFI Flash on the Expansion Bus */ { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, - IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* IXP425 PCI Configuration */ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* SDRAM Controller */ { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* PCI Memory Space */ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* Q-Mgr Memory Space */ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { 0 }, }; @@ -151,45 +151,45 @@ static const struct arm_devmap_entry ixp static const struct arm_devmap_entry ixp435_devmap[] = { /* Physical/Virtual address for I/O space */ { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* IXP425 PCI Configuration */ { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* DDRII Controller NB: mapped same place as IXP425 */ { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* PCI Memory Space */ { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* Q-Mgr Memory Space */ { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* CFI Flash on the Expansion Bus */ { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, - IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* USB1 Memory Space */ { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* USB2 Memory Space */ { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* GPS Memory Space */ { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, /* RS485 Memory Space */ { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, + VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { 0 } }; Modified: head/sys/arm/xscale/pxa/pxa_machdep.c ============================================================================== --- head/sys/arm/xscale/pxa/pxa_machdep.c Sat May 10 19:47:54 2014 (r265851) +++ head/sys/arm/xscale/pxa/pxa_machdep.c Sat May 10 20:03:03 2014 (r265852) @@ -129,7 +129,7 @@ static const struct arm_devmap_entry pxa PXA2X0_PERIPH_START, PXA250_PERIPH_END - PXA2X0_PERIPH_START, VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, + PTE_DEVICE, }, { 0, 0, 0, 0, 0, } };