From owner-freebsd-arch Tue Jan 15 21:13:15 2002 Delivered-To: freebsd-arch@freebsd.org Received: from netau1.alcanet.com.au (ntp.alcanet.com.au [203.62.196.27]) by hub.freebsd.org (Postfix) with ESMTP id 2BB8537B405; Tue, 15 Jan 2002 21:13:07 -0800 (PST) Received: from mfg1.cim.alcatel.com.au (mfg1.cim.alcatel.com.au [139.188.23.1]) by netau1.alcanet.com.au (8.9.3 (PHNE_22672)/8.9.3) with ESMTP id QAA03959; Wed, 16 Jan 2002 16:12:55 +1100 (EDT) Received: from gsmx07.alcatel.com.au by cim.alcatel.com.au (PMDF V5.2-32 #37641) with ESMTP id <01KD58A8B3WWVFKCPE@cim.alcatel.com.au>; Wed, 16 Jan 2002 16:13:10 +1100 Received: (from jeremyp@localhost) by gsmx07.alcatel.com.au (8.11.6/8.11.6) id g0G5Cp374428; Wed, 16 Jan 2002 16:12:51 +1100 Content-return: prohibited Date: Wed, 16 Jan 2002 16:12:51 +1100 From: Peter Jeremy Subject: Re: 64 bit counters again In-reply-to: ; from jhb@FreeBSD.org on Tue, Jan 15, 2002 at 05:21:37PM -0800 To: John Baldwin Cc: arch@FreeBSD.org, Thomas Hurst , "James E. Housley" , Bosko Milekic , Michal Mertl , Terry Lambert Mail-Followup-To: John Baldwin , arch@FreeBSD.org, Thomas Hurst , "James E. Housley" , Bosko Milekic , Michal Mertl , Terry Lambert Message-id: <20020116161251.E72285@gsmx07.alcatel.com.au> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-disposition: inline User-Agent: Mutt/1.2.5i References: <20020116120611.A72285@gsmx07.alcatel.com.au> Sender: owner-freebsd-arch@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On 2002-Jan-15 17:21:37 -0800, John Baldwin wrote: > >On 16-Jan-02 Peter Jeremy wrote: >> For the read case, the reader uses something like: >> >> loop: movl 4(mem),%edx >> movl (mem),%eax >> cmpl 4(mem),%edx >> jnz loop >> >> If an interrupt updates the MSW then you take another pass around the >> loop, otherwise you always read the correct value. >> >> For the SMP case, you either need to use locks or you need to use >> per-CPU counters. (And the per-CPU counters can be read by another >> CPU using the above trick). My parenthetical comment also neglects the effect of per-CPU caches :-(. >Well, SMP on Pentium's maybe, but not on Alpha, sparc64, or ia64, all of which >support OOE and looser memory models than x86, Good point. The multi-precision counters part is probably only relevant to IA32 (at least until we need 128-bit counters), but combining per-CPU counters will be needed in all SMP cases. I think I'll retract my suggestion that it's possible to read the counters on any CPU without locking :-). Locking per-CPU counters defeats most of the justification for having per-CPU counters in the first place. (There is still some advantage - the counters hopefully stay in the local CPU cache instead of continually jumping between caches). How about the following: Have a per-CPU thread to read the per-CPU counters and update them into common counters. This could be done either by having the counter read operation schedule a read on each CPU and then returning the total, or having a "counter update" thread that runs in each CPU every (say) second [with a degree of time skew] and does locked updates into a common central counter. Peter To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message