From owner-svn-src-all@FreeBSD.ORG Sat Jan 3 06:56:00 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 83A45B00; Sat, 3 Jan 2015 06:56:00 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 64B88E9E; Sat, 3 Jan 2015 06:56:00 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t036u00X041793; Sat, 3 Jan 2015 06:56:00 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t036txlJ041790; Sat, 3 Jan 2015 06:55:59 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201501030655.t036txlJ041790@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sat, 3 Jan 2015 06:55:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r276610 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Jan 2015 06:56:00 -0000 Author: adrian Date: Sat Jan 3 06:55:58 2015 New Revision: 276610 URL: https://svnweb.freebsd.org/changeset/base/276610 Log: Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT Modified: head/sys/mips/atheros/ar71xx_cpudef.h head/sys/mips/atheros/ar934x_chip.c Modified: head/sys/mips/atheros/ar71xx_cpudef.h ============================================================================== --- head/sys/mips/atheros/ar71xx_cpudef.h Sat Jan 3 06:35:53 2015 (r276609) +++ head/sys/mips/atheros/ar71xx_cpudef.h Sat Jan 3 06:55:58 2015 (r276610) @@ -65,6 +65,8 @@ struct ar71xx_cpu_def { void (* ar71xx_chip_init_gmac) (void); void (* ar71xx_chip_reset_nfc) (int); + + void (* ar71xx_chip_gpio_out_configure) (int, uint8_t); }; extern struct ar71xx_cpu_def * ar71xx_cpu_ops; @@ -149,6 +151,12 @@ static inline void ar71xx_reset_nfc(int ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active); } +static inline void ar71xx_gpio_ouput_configure(int gpio, uint8_t func) +{ + if (ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure) + ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure(gpio, func); +} + /* XXX shouldn't be here! */ extern uint32_t u_ar71xx_refclk; extern uint32_t u_ar71xx_cpu_freq; Modified: head/sys/mips/atheros/ar934x_chip.c ============================================================================== --- head/sys/mips/atheros/ar934x_chip.c Sat Jan 3 06:35:53 2015 (r276609) +++ head/sys/mips/atheros/ar934x_chip.c Sat Jan 3 06:55:58 2015 (r276610) @@ -417,6 +417,37 @@ ar934x_chip_reset_nfc(int active) } } +/* + * Configure the GPIO output mux setup. + * + * The AR934x introduced an output mux which allowed + * certain functions to be configured on any pin. + * Specifically, the switch PHY link LEDs and + * WMAC external RX LNA switches are not limited to + * a specific GPIO pin. + */ +static void +ar934x_chip_gpio_output_configure(int gpio, uint8_t func) +{ + uint32_t reg, s; + uint32_t t; + + if (gpio > AR934X_GPIO_COUNT) + return; + + reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); + s = 8 * (gpio % 4); + + /* read-modify-write */ + t = ATH_READ_REG(AR71XX_GPIO_BASE + reg); + t &= ~(0xff << s); + t |= func << s; + ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t); + + /* flush write */ + ATH_READ_REG(AR71XX_GPIO_BASE + reg); +} + struct ar71xx_cpu_def ar934x_chip_def = { &ar934x_chip_detect_mem_size, &ar934x_chip_detect_sys_frequency, @@ -434,4 +465,5 @@ struct ar71xx_cpu_def ar934x_chip_def = &ar934x_chip_reset_wmac, &ar934x_chip_init_gmac, &ar934x_chip_reset_nfc, + &ar934x_chip_gpio_output_configure, };